Design a combinational circuit with three inputs x, y, z and three outputs A, B, C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4 5, 6, or 7, the binary output is one less than the input.

Computer Networking: A Top-Down Approach (7th Edition)
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Chapter1: Computer Networks And The Internet
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consider what you would do for A, B, and C individually. Refer to the D latch diagram. For the given clock and D signals, what is the resulting output at Q? For the D register, using the same clock and D signals, what is the resulting outputs at -QL and QR? You can use the dashed boxes shown under the given signals for your answers, though you should provide a written explanation, too.

 

Note: -Q is the same thing as Q'
-Q
D
CLK = 1
D
Q
When CLK =1, the select line of the left-most tri-state buffer is 1,
and the select line of the other tri-state buffer is 0. Thus,
the value of D' appears at -Q, while the value (D’)' appears at Q.
%3D
CLK
Q
Positive-level-sensitive D latch
D
CLK = 0
closed
Q
connection
switch
Tri-state buffer
(connection)
When CLK=0, the select inputs are opposite from above. So the value of
D does not matter, since it is not connected.
The OLD value of D, however, is fed back to the circuit.
open
switch
inverter
(no connection)
Copyright Michael Weeks 2004, 2014
This is a level-sensitive latch since the state of the output is dependent on the level of the clock signal.
Transcribed Image Text:Note: -Q is the same thing as Q' -Q D CLK = 1 D Q When CLK =1, the select line of the left-most tri-state buffer is 1, and the select line of the other tri-state buffer is 0. Thus, the value of D' appears at -Q, while the value (D’)' appears at Q. %3D CLK Q Positive-level-sensitive D latch D CLK = 0 closed Q connection switch Tri-state buffer (connection) When CLK=0, the select inputs are opposite from above. So the value of D does not matter, since it is not connected. The OLD value of D, however, is fed back to the circuit. open switch inverter (no connection) Copyright Michael Weeks 2004, 2014 This is a level-sensitive latch since the state of the output is dependent on the level of the clock signal.
Design a combinational circuit with three inputs x, y, z and three outputs
A, B, C. When the binary input is 0, 1, 2, or 3, the binary output is one greater
than the input. When the binary input is 4 5, 6, or 7, the binary output is
one less than the input.
1-16.
Transcribed Image Text:Design a combinational circuit with three inputs x, y, z and three outputs A, B, C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4 5, 6, or 7, the binary output is one less than the input. 1-16.
Expert Solution
Step 1

Well, you have not told us the weights. I am going to assume that xyz represents

 

x * 2^2 + y * 2^1 + z * 2^0

 

and that the outputs represent

 

A * 2^2 + B * 2^1 + C * 2^0

 

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