Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs specified in Figure 2. Clearly show the timings in your waveforms.

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Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs
specified in Figure 2. Clearly show the timings in your waveforms.
Transcribed Image Text:Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs specified in Figure 2. Clearly show the timings in your waveforms.
module test (clk, a, b, f, g, h);
input clk, a, b;
output f, g, h;
reg f, g, h;
always@ (negedge glk)
f <= #5
a| b;
alwayse (clk)
g = #10 f ^ b;
alwayse (f or g)
h = #2 f & g;
endmodule
Figure 1
Transcribed Image Text:module test (clk, a, b, f, g, h); input clk, a, b; output f, g, h; reg f, g, h; always@ (negedge glk) f <= #5 a| b; alwayse (clk) g = #10 f ^ b; alwayse (f or g) h = #2 f & g; endmodule Figure 1
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