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A system with simple paged memory management has addresses of B bits and pages of size P KiB. If all memory is pageable, what is the maximum number of items contained in a process's page table? What if K KiB are reserved for the kernel and are not pageable? Also suppose that the page table is organized in 2 levels, so that the page directory (first level) is addressed by D bits. How many bits will be used to address the second level? How many entries will there be, at most, among all the tables of the pages (first and second level) of a process?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Consider an operating system using memory mapping on a page basis and using a single level page table. Assume that the necessary page table is always in memory. The system takes 200 ns to make a memory reference, how long does a paged memory reference take? Group of answer choices 400 ns (nanoseconds) 809.2 ms (microseconds) 200 ns (nanoseconds) 1638.4 ms (microseconds)Suppose the page table for the process currently executing on the processor looks like the following. All numbers are decimal, everything is numbered starting from zero, and all addresses are memory byte addresses. The page size is 1,024 bytes. Virtual page number 0 Valid bit Reference bit Modify bit Page frame number 1 1 0 1 1 7 2 0 0 0 3 1 0 0 2 4 0 0 0 5 1 0 1 0 What physical address, if any, would each of the following virtual addresses correspond to? (Do not try to handle any page faults, if any.) 1,052 2,221 5,499 Edit View Insert 12pt Paragraph Format Tools Table BIU Av
- Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?Consider a system with 256Mbytes of main memory with page size of 4Kbytes. It has a logical address space of 26-bits. Answer the following questions. (Assume byte-addressable memory) (i) How many of the 26-bits of the logical address represent page# and how many bits represent the offset? (ii) How many entries are there in a conventional single-level page table for a process? (iii) How many entries are there in an inverted page table?For an old computing system with 2K bytes physical memory, and the virtual address has 13bits. Suppose that the size of page/frame is 256 bytes. For a process A, it has its codes and data inpage 0, 1, 2, 10, 11, 28, 29, where pages 0, 1, 10, 29 are in frame 1, 3, 4 and 6, respectively.Moreover, frame 0 contains kernel OS code/data and all other frames are free.a. Show the page table and the content of each PTE for process A;b. Use a figure to illustrate the address translation for virtual address 1110000100000 and explainwhat happens during the translation (interaction among page table, physical memory, disk, andoperating system);c. Suppose that there is a TLB with 4 entries and the current content has the mapping informationfor pages 0, 1. Draw a new figure to illustrate the translation of address 101000011000 andexplain what happens during the translation process.
- Consider a memory-management system based on paging. The total size of the physical address space 64 MB, Pages of size 4 KB, the Logical address space of 4GB. total number of pages are 16384, total number of frames are 16384 and the number of entries in a page table are 1048576.Now Calculate: a)Size of Page Table b) No of bits in Physical Address c) No of Bits in Logical AddressSuppose you have a byte-addressable virtual address memory system with 32 virtual pages of 32 bytes each, and 8 page frames. Assuming the following page table, answer the questions below: | Page # | Frame # | Valid bit ||--------|---------|-----------|| 0 | 4 | 1 || 1 | 3 | 1 || 2 | - | 0 || 3 | 0 | 0 || 4 | 1 | 1 || 11 | 6 | 0 || 13 | 7 | 1 || 17 | - | 0 | a) How many bits are needed to address this virtual memory? b) What is the size of the Page field? c) What is the size of the Offset field? d) What is the size of the Page Frame field? e) What is the maximum number of the entries in this Page Table? f) What Physical address corresponds to the Virtual address 0x22? Answer should be in hexadecimal number. (if the address causes a page fault, answer as "page fault" with the proper reason) g) What Physical address corresponds to the…Suppose you have a byte-addressable virtual address memory system with 32 virtual pages of 32 bytes each, and 8 page frames. Assuming the following page table, answer the questions below: | Page # | Frame # | Valid bit ||--------|---------|-----------|| 0 | 4 | 1 || 1 | 3 | 1 || 2 | - | 0 || 3 | 0 | 0 || 4 | 1 | 1 || 11 | 6 | 0 || 13 | 7 | 1 || 17 | - | 0 |a) How many bits are needed to address this virtual memory? b) What is the size of the Page field? c) What is the size of the Offset field? d) What is the size of the Page Frame field?
- Suppose we have a system with 8-byte words and a cache with 32-byte blocks connected directly to memory. The cache has a hit time of 10 ns. The bus to memory is 8 bytes wide, requesting a word from memory takes 100 ns (total, aka round trip time), and memory bus transactions are serialized (not pipelined). The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only 20%. Show your work. (a) What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block (25% chance of each). This means that 25% of misses are for word 1 in a block, 25% for word 2, 25% for word 3, and 25% for word 4. (b) What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is 5%, 15%, 30%, and 50%, respectively? (c) What is the AAT speedup over baseline with…A computer with a 32-bit address uses a two-level page table. Virtual addresses are split into a 9-bit top-level page table field, an 11-bit second-level page table field, and an offset. How large are the pages and how many are there in the address space?Unlike a byte that is always 8 bits, word size can vary from machine to machine. Let's say we have a 16-bit system (word size is 2 bytes) and a memory unit that has 10 address lines. Because there are 10 address bits, we can have 210 unique addresses, hence 1024 addresses. If we are working with something word-addressable, that means each word has a unique address, and we canstore 1024 words. The memory size is 1 kiloword, or equivalently, 2kilobytes because each word is 2 bytes long. The address of the first word is 0, the second word is 1, the third word is 2, and the last word is 1023.Now, with 4 address lines and a word size of 4 bits, what is the address of the last word?
