et assume that it is required to install 5 capacitor banks with a given maximum capacity for each of hem at 5 different buses of a 33-bus distribution network using genetic algorithm. The question is hat what would be genetic algorithm chromosome for solving the optimization process?
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- WSNs communicate. Through the use of sensor nodes, WSNs may connect with base stations. Processing and memory on sensor nodes are severely constrained. Consider a decomposable algorithm. To solve these subproblems at the sensor nodes, should we use the divide-and-conquer strategy or dynamic programming? Conciseness is a virtue in writing?Q1. Give a comparison of FIFO, LRU and OPTIMAL algorithms in term of Page faults with three and four frames in each case for the reference string of pages duly demanded in Main Memory. Reference String: 2, 3, 3, 2, 1, 4, 0, 0, 3, 2, 1, 1, 2, 3, 4Consider a swapping system in which memory consists of the following hole sizes inmemory order: 12 MB, 4 MB, 20 MB, 12 MB,18 MB, 7 MB, 9 MB and 12 MB.Which hole is taken for successive segment requests of(a) 10MB(b) 15MB(c) 9 MBfor first fit, worst fit, and next fit?
- Using Dijkstra’s algorithm, and showing your work using a table similar to Table 5.1 , do the following: a. Compute the shortest path from t to all network nodes.4.25 Consider the following loop. LOOP: lw $s0, 0($s3) lw $s1, 8($s3) add $s2, $s0, $s1 addi $s3, $s3, -16 bnez $s2, LOOP Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, that the pipeline has full forwarding support, and that branches are resolved in the EX (as opposed to the ID) stage. 4.25.1 [10] <§4.8> Show a pipeline execution diagram for the first two iterations of this loop. Mark pipeline stages that do not perform useful work.Consider the following failure model for faulty processors. Processors follow the protocol but might fail at unexpected points of time. When processors fail, they simply stop functioning and do not continue to participate in the distributed system. Given such a failure model, design an algorithm for reaching agreement among a set of processors. Discuss the conditions under which agreement could be reached. Present your algorithm as a pseudocode.
- Consider the following failure model for faulty processors. Processors follow the protocol but might fail at unexpected points of time. When processors fail, they simply stop functioning and do not continue to participate in the distributed system. Given such a failure model, design an algorithm for reaching agreement among a set of processors. Discuss the conditions under which agreement could be reached. Present your algorithm as a pseudocode. Please write in your own solutionA demand paging system takes 100 time units to service a page fault and 300 time units to replace a dirty page. Memory access time is 1 time unit. The probability of a page fault is p. In case of a page fault, the probability of page being dirty is also p. It is observed that the average access time is 3 time units. Then the value of p is?Computer Science Question: Consider a virtual cylinder identical to the one shown the figure below with the following characteristics: seek time is 4 ms/track, search time is 1.7 ms/sector, and data transfer time is 0.9 ms. Calculate the resulting seek time, search time, data transfer time, and total time for the following Request List, assuming that the read/write head begins at Track 0, Sector 0. Finally, calculate the total time required to meet all of these requests. Track Sector 1 0 1 4 1 0 3 1 2 4 3 0
- The previous problem is in the picture. Suppose that I have 800 Gigabytes worth of movies on my hard drive at home, and I’d like to get them to a friend in Chicago. I could either send them over the Internet, or I could copy them to a thumb drive, drive to Chicago, and deliver them by hand. Assume that the specs for my cable connection are the same as in the previous problem, but the friend in Chicago has a cable connection which gets 25 Mbps down/5 Mbps up. Which would be faster? Show your work.In this exercise, we examine how pipelining aff ects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150ps 300ps 200ps Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 45% 20% 20% 15% What is the clock cycle time in a pipelined and non-pipelined processor?What is the total latency of an LW instruction in a pipelined and non-pipelined processor?If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?Assuming there are no stalls or hazards, what is the utilization of the data memory?Assuming there are no stalls or hazards, what is the utilization of the write-register port of the “Registers” unit?Instead of a single-cycle organization, we can use a…Use Table 11-2 to solve the problem. The requirement for computer server capacity at a particular company is expected to increase at a rate of 15% per year for the next 5 years. If the server capacity is expected to be 1,200 gigabytes in 5 years, how many gigabytes of capacity are there today? Round to the nearest whole gigabyte.