Exercise 5: Self-modifying programs - Uniformity .data 1. Can we modify the order of executing the instructions to improve the performance of a pipeline? list: word 2, 3, 5, 7, 11, 13, 17, 19, 23, 29 size: word 10 .text 2. Using the table below, show how the instructions will flow through the pipeline a 5-state pipeline when we have Uniformity. $t3, size $t1, list $t2,0 $t4, ($t1) $t1, $t1, 4 Iw la li Iw addi 11

Exercise 5: Self-modifying programs - Uniformity .data 1. Can we modify the order of executing the instructions to improve the performance of a pipeline? list: word 2, 3, 5, 7, 11, 13, 17, 19, 23, 29 size: word 10 .text 2. Using the table below, show how the instructions will flow through the pipeline a 5-state pipeline when we have Uniformity. $t3, size $t1, list $t2,0 $t4, ($t1) $t1, $t1, 4 Iw la li Iw addi 11

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Please give a step-by-step solution. Do not provide a wrong solution or copy-paste a solution from sites like Chegg. I need the right solution to the given question. Question: For the instructions below, remove the pipeline hazards using i) Stalling, ii) Stalling +Forwarding and iii) Stalling + Forwarding +Code Scheduling. Also, show the CPI for eachstage.LW $t0, 4($t1)SLL $t0, $t0, 2SW $t1, 4($t3)ADDI $t1, $t0, 2SLL $s1, $s1, 4LW $t1, 4($t0)
lw r1,12(r7)lw r2,16(r7)add r1,r1,r2sw r1,4(r5)a. Identify and describe all the data dependencies.b. How many clock cycles does it take to execute this code without any pipelining?c. How many clock cycles with pipelining, but no bypassing (stalls cause the pipeline to wait until previous instruction is finished)?
Is it still feasible to accomplish pipelined execution even if the time it takes to execute pipeline instructions is not balanced? Where can you perceive the inefficiencies in this situation?
It is possible to teach compilers and assemblers to sequence assembly language instructions in a manner that poses the least possible danger to a pipeline. One of the purposes of a pipeline's layout is to achieve this. Do all assemblers and compilers rearrange assembly language instructions in the same manner to maximize efficiency?
The runtimes of the five stages of executing an instruction in a non-pipelined machine are listed below. Instruction Fetch 100ps Instruction Decode 200ps ALU 300ps Memory 300ps Write Back 200ps This is then converted into a pipelined machine M1 using the most critical stage as the cycle time. For a new machine M2, we are allowed to break up exactly one stage into two substages of equal times giving us a six stage pipeline. A1: Discuss in short clear sentences the latency differences between the machines M1 and M2. A2: Discuss in short clear sentences the throughput differences between the machines M1 and M2.
Can pipelined execution be achieved if the execution duration of pipeline instructions is not balanced? What ineffectiveness do you observe?
Can pipelined execution be achieved if the execution time of pipeline instructions is not balanced? What ineffectiveness do you observe?
When we execute such a program:(1) R1 = 3 + 5(2) R2 = R1 / 4(3) R3 = 4 * 16(4) R4 = R3 * 2We realize a problem in the pipeline of Teletraan-2. Instruction (2) will be waiting for the resultgenerated by Instruction (1). That means the operand fetch stage cannot fetch the operand ofInstruction (2) from R1, unless the write back stage finishes writing the result of Instruction (1)into R1. As a result, the pipeline is stalled for 3 CPU clock cycles. What should we do toalleviate the problem?A. Nothing. We will have to let Instructions (2), (3), and (4) wait.B. We will put Instructions (2), (3), and (4) in a queue. The first instruction whose operandsare ready will be issued and executed. In this case, Instruction (3) will be the nextinstruction executed after Instruction (1).C. We will put Instructions (2), (3), and (4) in a queue. The first instruction whose operandsare ready will be issued and executed. In this case, Instruction (4) will be the nextinstruction executed after Instruction…
Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?
If the execution times of the pipeline instructions are not balanced, is pipelined execution still possible? Where do you see the inefficiencies here?
Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers (see image 1). Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage. If we have a simple scalar pipeline but allow out-of-order execution, we can construct the following table for the execution of the first seven instructions (see image 2). The entries under the four pipeline stages indicate the clock cycle at which each instruction begins each phase. In this program, the second ADD instruction (instruction 3) depends on the LOAD instruction (instruction 1) for one of its operands, r6. Because the LOAD instruction takes five clock cycles, and…
Discuss the limitations and trade-offs in increasing the pipeline depth in a CPU. What factors should be considered when determining the optimal pipeline depth?