column width=15Appendix AFetch and decodecolumn width=26column=10 column width=15column width=26InstructionBoolean conditionRTLnameFetchTO)L:AR<--PC, SC<-- 0TI)L:IR<-- M[AR].PC<--PC+1(DO:D7) <--IR(12:14), I<-- IR(15),rowDecodeT2)L:AR<-- IR(0:11)hight-30IndirectD7'.LT3)L:AR<--M[AR]Input/output instructionsInstruction Hexadecimal Boolean conditionRTLINPF800(D7.I.T3.IR(11))L:AC(0:7) <-. INPR,OUTF400(D7.I.T3.IR(10))L:OUT <-- AC(0:7), SC <-- 0SKIF200(D7.I.T3.IR(9))L:(FGI)L:PC <-- PC+1,SC <-- 0SKOF100(D7.1.T3.IR(8))L:(FGO)L:PC <- PC+1,SC <-- 0IONFO80(D7.1.T3.IR(7))L:IEN <-- 1, SC<.. 0IOFF040(D7.I.T3.IR(6)L:IEN <.. 0, SC<.. 0Register reference instructionsInstructionMemory reference instructionsHexdecimal Boolean conditionInstruction HexadecimalBoolean conditionRTLRTLCLA7800D7.1.T3.IR(11))L:AC <-- (0000), SC <-- 0AND(0, 8)хххDO.T4)L:DR <-- M[AR]CLE7400(D7.1.T3.IR(10))L:E <-- (0), SC <.-0DO.TS)L:AC <-- (AC.DR)L, SC <-- 0CMA7200(D7.1.T3.IR(9))L:AC <-- AC', SC <-- 0ADD(1,9)хххDI.T4)L:DR <-- M[AR]СМЕ7100(D7.1'.T3.IR(8))LE <--E',SC <--0DI.T5)L:AC <--(AC+DR), SC <-- 0CIR7080(D7.1.T3.IR(7))L:AC(14:0) <.. AC(15:1),AC(15) <-- E,E <-- AC(0). SC <--LDA(2, A)xxxD2.T4)L:DR <-- M[AR]CIL7040(D7.1.T3.IR(6))L:AC(15:1) <-- AC(14:0),D2.T5)L:AC <-- DR, SC <-- 0AC(0) <.- E, E <.- AC(15), SC <. 0INC7020(D7.1.T3.IR(5))L:AC <-- AC+1, SC <-- 0STA(3. В)хххD3.T4)L:M[AR] <-- AC, SC <-- 0SPA7010(D7.1.T3.IR(4)L: (AC(15)")L:PC <-- PC+1,SC <.-BUN(4, С)хххD4.T4 )L:PC <--AR, SC <-- 0(D7.1'.T3.IR(3))L: (AC(15))L:PC <-- PC+1, SC <-- 0SNA7008SZA7004(D7.r.T3.IR(2))L:: (AC=(0000))L:PC <.. PC+1, SC <.- (BSA(5, D)xxDS.T4)L:M[AR] <-- PC, AR <-- AR+1DS.T5)L:PC <-- AR, SC <-- 0SZE7002(D7.1.T3.IR(1))L: (E=0)L:PC <-- PC+1,SC <-- 0ISZ(6, E)xxxD6.T4)L:DR <.. M[AR]HALT7001(D7.I.T3.IR(0))L:S <-- 0, SC <-- 0D6.T5)L:DR <-- DR+1M[AR]<-- DR, SC <-- 0,(DR=0000)L:PC<-- PC+1)row hight=30D6.T6)L: The initial contents of the basic computer registers and memory are shown below. The table show the instruction fetching stage. You may use the tables in AppendixA.Complete the highlighted cells in Table.1Table.1 Basic computer register contents (all values are in hexadecimalControl condition Register TransferD7 EACDRIRPCARM[AR]000 195C,000 195C,000 195C,294C,200,Initial ValuesInitial Values1041,430,1227294C,1041,430,31C,8960,TO:AR<--- PC294C,1041,430,430,7200,T1:IR<--- M[AR), PC <--- PC+1T2:AR<--- IR(0-11), I<---IR(15),D0:D7<---IR(14:12)column width=16column width=40To set column width go the top row above rowl click the right mouse on column and set column width to see all the content of the column

RTL I E AC DR IR PC AR M[AR] Initial Value 0 0 3024 3015 3015 314…

Fetch and decode Instruction Boolean condition RTL name Fetch TO)L: AR<--PC, SC<-- 0 TI)L: IR<.- M[AR].PC<-PC+1 (DO:D7) <--IR(12:14), I<-- IR(15), AR<-- IR(0:11) row Decode T2)L: hight-30 Indirect D7 L.T3)L: AR<--M[AR] Input/output instructions Instruction Hexadecimal Boolean condition RTL INP F800 (D7.I.T3.IR(11))L: AC(0:7) <-- INPR, OUT <-- AC(0:7), SC <-- 0 (FGI)L:PC <-- PC+1,SC <-- 0 (FGO)L:PC <-- PC+1,SC <-- 0 IEN <--1, SC<- o OUT F400 (D7.L.T3.IR(10))L: SKI F200 (D7.L.T3.IR(9))L: SKO F100 (D7.L.T3.IR(8))L: ION FO80 (D7.LT3.IR(7))L: IOF F040 (D7.L.T3.IR(6))L: IEN < 0, SC<. 0

Fetch and decode Instruction Boolean condition RTL name Fetch TO)L: AR<--PC, SC<-- 0 TI)L: IR<.- M[AR].PC<-PC+1 (DO:D7) <--IR(12:14), I<-- IR(15), AR<-- IR(0:11) row Decode T2)L: hight-30 Indirect D7 L.T3)L: AR<--M[AR] Input/output instructions Instruction Hexadecimal Boolean condition RTL INP F800 (D7.I.T3.IR(11))L: AC(0:7) <-- INPR, OUT <-- AC(0:7), SC <-- 0 (FGI)L:PC <-- PC+1,SC <-- 0 (FGO)L:PC <-- PC+1,SC <-- 0 IEN <--1, SC<- o OUT F400 (D7.L.T3.IR(10))L: SKI F200 (D7.L.T3.IR(9))L: SKO F100 (D7.L.T3.IR(8))L: ION FO80 (D7.LT3.IR(7))L: IOF F040 (D7.L.T3.IR(6))L: IEN < 0, SC<. 0

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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