Figure 2 shows the logic symbol of the 3-to-8 binary decoder, the 74x138. 74x138 YO O- YO_L Y1 O- Y1_L Y2 O- Y2_L Y3 0 Y4 0 Y5 0 Y6 O- Y6_L Y7 O- Y7_L G1 G1 O G2A O G2B G2A_L - G2B_L Y3 L Figure 2 Y4 L A A Y5 L
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- The Excess-3 coding system is a four-bit digital coding system for encoding all decimal digits from 0 to 9. To encode a decimal digit, we add three to it and then convert the result to binary. A valid code has the following range:1. Minimum = 0011, encoding decimal 0( 0 + 3 = 3 = 0011)2. Maximum = 1100, encoding decimal 9(9 + 3 =12 = 1100)Design a logic circuit that will detect an error if a four-bit number is not a valid Excess-3 number. (Hint: Use four input variables to represent the four bits of the Excess_3 number. If the combination of the input bits is 0000,0001,0010,1101,1110, or 1111, the output will be HIGH. For all other cases, the output will be LOW.)Design a sequence detector for the bit pattern “101010”.- Work out the state diagram in a similar way.- Then code the state diagram in Verilog. PLEASE CODE THE STATE DIAGRAM IN VERILOG!In an 8-bit computer, the representation of -75 in the one's complement encoding is: a)10110100 b)11001011 c)11110101
- Sketch the following signals Biphase L, Biphase M, Biphase S, Bi polar and Diff. Manchester using binary data 0010 1001In a digital system, only binary numbers in the form of 0 and 1 are represented. As a student of digital logic design, convert the decimal number 4798.67510 to hexadecimal (base 16) and then convert the hexadecimal number obtained to binaryWrite the equivalent VRC and LRC in the given below. Odd Parity for VRC and Even for LRC. Indicate the character that should be attached in the given. Given: (Using Hex) D - 44i - 69e - 65c - 63i - 69l - 6Cy - 79n - 6Espace - 20 G - 47o - 6Fn - 6Ez - 7Aa - 61l - 6Ce - 65s - 73 Please use the ASCII Table.
- design the following circuits, for 4 bit binary input(0000-1111): ● a circuit that can detect prime numbers ● a circuit that can detect fibonacci numbers ● a circuit that can detect tribonacci numbers ● a circuit to detect catalan numbers between 0-15Computer Architecture Given the below IEEE single precision FP format: 1-bit Sign 8-bit Biased Exponent 23-bit Mantissa Bias = 127 Convert IEEE 32-bit FP number (1011 0100 1000 1100 0011 0000 0000 0000)2 to decimalFinal Expression = x4'x3'x2'x1' + x4x3x2'x1' + x4x3'x2x1' + x4x3'x2'x1 + x4'x3x2x1' + x4'x3x2'x1 + x4'x3'x2x1 + x4x3x2x1 This expression needs simplification with boolean algebra
- Write the equivalent VRC and LRC in the given below. Odd Parity for VRC and Even Parity for LRC. Indicate the character that should be attached in the given. Given: (Using Hex) D - 44i - 69e - 65c - 63i - 69l - 6Cy - 79n - 6Espace - 20 G - 47o - 6Fn - 6Ez - 7Aa - 61l - 6Ce - 65s - 73 Please use the ASCII Table.Consider an S-box that takes 8 bits as input and generates a 2-bit output. The first and second bits of the input are XOR-ed to give the first bit of the output. The seventh and eighth bits of the input are XOR-ed to give the last bit of the output. What is the output if the input is 11000111?1. Convert 53 base 10 to binary. 2. Convert 10111011012 to hexadecimal. 3. Convert 0.575 base 10 to binary. 4. Convert 0.312510 to hexadecimal. 5. Convert 0.3125 base 10 to octal. (Our lesson is LOGIC CIRCUITS AND SWITCHING THEORY)