A synchronous state machine has two inputs (X1 and X2) and two outputs (Z1 and Z2). The inputs epresent a 2-bit binary number (N). If the present value of (N) plus the previous value of (N) is greater than (2), then (Z1=1). If the present value of (N) times the previous value of (N) is greater than (2), then (Z2=1). Otherwise, (Z1Z2=O0). When the

A synchronous state machine has two inputs (X1 and X2) and two outputs (Z1 and Z2). The inputs epresent a 2-bit binary number (N). If the present value of (N) plus the previous value of (N) is greater than (2), then (Z1=1). If the present value of (N) times the previous value of (N) is greater than (2), then (Z2=1). Otherwise, (Z1Z2=O0). When the

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter3: Data Representation

Section: Chapter Questions

Problem 27VE: Data represented in ________ is transmitted accurately between computer equipment from different...

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Suppose we are working with an error-correcting code that will allow all single-bit errors to be corrected for memory words of length 7. We have already calculated that we need 4 check bits, and the length of all code words will be 11. Code words are created according to the Hamming algorithm presented in the text. We now receive the following code word: 1 0 1 0 1 0 1 1 1 1 0 Assuming even parity, is this a legal code word? If not, according to our error-correcting code, where is the error?
Suppose we are working with an error-correcting code that will allow all single-bit errors to be corrected for memory words of length 7. We have already calculated that we need 4 check bits, and the length of all code words will be 11. Code words are created according to the Hamming algorithm presented in the text. We now receive the following code word: 1 0 1 0 1 0 1 0 1 1 0 Assuming odd parity, is this a legal code word? If not, according to our error-correcting code, where is the error?
We are provided an FP prototype labeled: IEEE 754-2015 of 15 bits similar to IEEE 754, where the exponent has size 6 bits and fraction has size 8 bits, and 1 MSB for the sign. No guard or round bits are assumed. What is the bias of the system? Find the smallest and largest number that can be represented. Find the new representation of the decimal number you worked with earlier (e.g., the 0.012).
Suppose we are working with an error-correcting code that will allow all single-bit errors to be corrected for memory words of length 12. a) How long should the check bits and why? b) Code words are created according to the Hamming Algorithm presented in the text. We now receive the following code word: 0 1 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 Assuming even parity, is this a legal code word? If not, according to our error-correcting code, where is the error? PLEASE SHOW ALL WORKING UNDERSTANDABLE THANK YOU
Suppose we are working with an error-correcting code that will allow all single-bit errors to be corrected for memory words of length 12. a) How long should the check bits and why? b) Code words are created according to the Hamming Algorithm presented in the text. We now receive the following code word: 0 1 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 Assuming even parity, is this a legal code word? If not, according to our error-correcting code, where is the error?
A Gray code is a sequence of binary numbers with the property that no more than 1 bit changes in going from one element of the sequence to another. For example, here is a 3-bit binary Gray code: 000, 001, 011, 010, 110, 111, 101, and 100. Using three D flip-flops and a PLA, construct a 3-bit Gray code counter that has two inputs: reset, which sets the counter to 000, and inc, which makes the counter go to the next value in the sequence. Note that the code is cyclic, so that the value after 100 in the sequence is 000.
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If the floating-point number representation on a certain system has a sign bit, a 3-bitexponent and a 4-bit significand: • What is the largest positive and the smallest positive number that can be stored on this?system if the storage is normalized? (Assume no bits are implied, there is no biasing,exponents use two's complement notation, and exponents of all zeros and all ones areallowed.)• What bias should be used in the exponent if we prefer all exponents to be non-negative?Why would you choose this bias? show work and write out solution
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