Figure 6 shows the circuit diagram for a single stage NMOS amplifier realized with the transistor MI. (a) What kind of amplifier is M1 part of? By using Miller's theorem draw the resulting small signal equivalent circuit and derive an expression for the voltage gain Gv at varying of the frequency f. Assume that the output impedance of the signal generator connected at the input of the circuit is Ro. (b) Derive the expression of the poles fpi in the gain G, and sketch the bode plot for the gain of the circuit stating any assumption. (c)

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Figure 6 shows the circuit diagram for a single stage NMOS amplifier realized with
the transistor M1.
Q6
(a)
What kind of amplifier is M1 part of?
By using Miller's theorem draw the resulting small signal equivalent circuit and
derive an expression for the voltage gain Gv at varying of the frequency
f. Assume that the output impedance of the signal generator connected at the
input of the circuit is Ro.
(b)
Derive the expression of the poles fpi in the gain G, and sketch the bode plot for
the gain of the circuit stating any assumption.
(c)
To properly bias the transistor in saturation RG = R1//R2> 2 k2 and the output
resistance of the generator connected at the input of the amplifier is Ro= 50 N.
Is it possible to design the amplifier choosing by RG to operate with constant
gain G, up to fpl = 5 kHz (flat response), if the parallel between the Miller's
equivalent capacitance CMI and Cgd connected between the gate and source is
Ci = CM1 // Cgd = 1 µF?
(d)
VDD
R1
RD
V OUt
M1
Vin
Cp
CG
RL
R2
CG
|Rs
Cs
V ss = 0 V
Figure 6
Transcribed Image Text:Figure 6 shows the circuit diagram for a single stage NMOS amplifier realized with the transistor M1. Q6 (a) What kind of amplifier is M1 part of? By using Miller's theorem draw the resulting small signal equivalent circuit and derive an expression for the voltage gain Gv at varying of the frequency f. Assume that the output impedance of the signal generator connected at the input of the circuit is Ro. (b) Derive the expression of the poles fpi in the gain G, and sketch the bode plot for the gain of the circuit stating any assumption. (c) To properly bias the transistor in saturation RG = R1//R2> 2 k2 and the output resistance of the generator connected at the input of the amplifier is Ro= 50 N. Is it possible to design the amplifier choosing by RG to operate with constant gain G, up to fpl = 5 kHz (flat response), if the parallel between the Miller's equivalent capacitance CMI and Cgd connected between the gate and source is Ci = CM1 // Cgd = 1 µF? (d) VDD R1 RD V OUt M1 Vin Cp CG RL R2 CG |Rs Cs V ss = 0 V Figure 6
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