For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter11: Operating Systems
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For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.
a. What is the cache block size in words?
b. How many entries does the cache have?
Tag
31-13
Index
12-6
Offset
5-0
Transcribed Image Text:For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
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