Given the PMOS circuit in the Figure below, with parameters as listed. VDD=6V, IVtpl = 0.7V, kp' = 0.3 mA/V², RG1 = 20kn, RG2 = 40kn, W/L=4. Assume λ = 0. RGI RG2 w ww VDD Rp im Q₂ Figure 2 VD

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Given the PMOS circuit in the Figure below, with parameters as listed.
VDD=6V, IVtpl = 0.7V, kp' = 0.3 mA/V², RG1 = 20kn, RG2 = 40kn,
W/L=4. Assume λ = 0.
RGI
RG2
w
M
VDD
Rp
Q₂
Figure 2
VD
Transcribed Image Text:Given the PMOS circuit in the Figure below, with parameters as listed. VDD=6V, IVtpl = 0.7V, kp' = 0.3 mA/V², RG1 = 20kn, RG2 = 40kn, W/L=4. Assume λ = 0. RGI RG2 w M VDD Rp Q₂ Figure 2 VD
What is VSG?
01 V
O 2V
O 3V
0 4V
Question 9
What is Vovl?
0.3 V
O 0.7 V
O 1.3 V
O 2.7 V
Question 10
What is the largest Ro to maintain saturation?
| 4.64ΚΩ
O 3,25k
Ο 1.07 Ω
Ο 0.75ΚΩ
Transcribed Image Text:What is VSG? 01 V O 2V O 3V 0 4V Question 9 What is Vovl? 0.3 V O 0.7 V O 1.3 V O 2.7 V Question 10 What is the largest Ro to maintain saturation? | 4.64ΚΩ O 3,25k Ο 1.07 Ω Ο 0.75ΚΩ
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