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- Realize the following function ; " on the image " using a(a) 4-to-1 multiplexer, and draw the logic diagram.(b) 8-to-1 multiplexer, and draw the logic diagram.You may use external gates if needed.An X-input exclusive-OR gate and a Y-input exclusive-OR gate (where X=3, Y=4 have their outputs connected to a 2-input exclusive-NORgate. Do the following:a) Draw the logic diagram and analyze the logic expression of the output (in standard SOPform).b) List out all essential prime implicants.what a logic function corresponds to the following arrangement? a.L =(S1 OR S2) AND (S3 OR S4)
- a) Build a karnaugh Map for this function table [[A, B, C, D, F b) What is the simplest minimum expression for this function c) Build a circuit using AND, OR, NOT gates to realize this logicBelow is a primary encoder truth table. In this table, D3 has the highest priority and D0 the lowest. Update this table so that D0 has the highest priority and D3 has the lowest priority and draw the logic diagram of the primary encoder based on this table.Implement the following logic function using only 3-8 decoders and logic gates. f(a,b,c,d ) Σ m(2,4,6,8,10,14,15)
- Draw logic diagrams (network of gates) of the circuits that implement the original and simplifiedexpressions of the following:a’bc + abc’ + abc + a’bc’You want to design an arithmetic comparison combined logic circuit. (a) List the steps that you will apply in the design approach. Design a 4-bit comparison (large-equal-small) circuit. Explain each step. With AND, OR, NOT gatesmake it happen. (b)By comparing the numbers 9 and 1 in the circuit you designed, the resultdiscuss.DIGITAL LOGICGiven the two binary numbers X = 1000100 and Y = 100101 , perform the subtraction X - Y by using 1's complement and 2's complement.
- Implement the following logic function using only 2 multiplexers 4 to 1. You can use Not and Or gates if necessary. f(A,B,C)=Π M (1,5,7)What type of logic circuit is represented by figure 4 shown below? Name the gate whose output is LOW if and only if all the inputs are HIGH. If an SR latch has S=1, R=0 initially. When the S input goes low, what will be the output?A logic function f(A,B,C) implemented with 4x1 MUX circuit. Implement the same function with using only one 4x1 MUX. (B and C are selection inputs B=S1; C=S0)