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- Question 1 a) i. A synchronous counter with 4-bit, uses flip-flops with propagation delay times of 15 ns each. What is the Maximum possible time required for change of state, and why? ii) Addition of decimal numbers can also be performed using excess–3 codes. Add 876 and 704 in excess–3 code. iii) Digital logic functions (equations) can be simplified using the theorems of Boolean algebra. The reduced Boolean expression helps in getting simple, less expensive and smaller circuit.Simplify and draw the logic diagram for the given expressionF = ABC+ ABC+ ABC+ ABC+ ABC.1. Obtain a logic data book and list down all the available multiplexers, decoders, and decoder/demultiplexers. 2. Show how 74251 8-to-1 line multiplexers may be connected to implement a 16-to-1 MUX. 3. What are the advantages and disadvantages of the MUX and the decoder methods over one another? 4. Describe how a combinational circuit may be implemented using decoders given the minterm list form of two functions. 5. What are the advantages and disadvantages of the MUX and the decoder methods over conventional methods of implementing a function using logic gates?3. Implement the following Boolean function with a 4 x1 multiplexer and external gates.(a)?1 = ∑(1, B, 4, C, A, 11, 12, 13, 14, 15)(b) ?2 = ∏(1, 2, B, C, 5, 7, 8, 10, 11, 13, 15)
- 1. DESIGN A COMBINATIONAL CIRCUIT THAT GENERATES THE 9'S COMPLEMENT OF A BCD DIGIT.2 DESING A COMBINATIONAL CIRCUIT THAT COMPARES TWO 4-BIT NUMBERS B AND C TO CHECK IF THEY ARE EQUAL. THE CIRCUIT HAS ONE OUTPUT, Z, SO THAT Z = 1 IF B = C AND Z = 0 IF B IS NOT EQUAL TO B.3. A COMBINATIONAL CIRCUIT IS DEFINED BY THE FOLLOWING THREE BOOLEAN FUNCTIONS. DESIGN THE CIRCUIT WITH A DECODER AND EXTERNAL GATES F1= X'Y'Z' + XZ F2= XY'Z' + X'Y F3= X'Y'Z + XY *HINT: OBTAIN THE KMAP AND TRUTH TABLEPROBLEM: In a simple copy machine, a stop signal, S, is to be generated to stop the machine operation and energize an indicator light whenever either of the following conditions exists: (A) there is no paper in the paper feeder tray; (B) the two microswitches in the paper path are activated, indicating a jam in the paper path. The presence of paper in the feeder tray is indicated by a HIGH at logic signal P. Each of the microswitches produces a logic signal (Q and R) that goes HIGH whenever paper is passing over the switch to activate it. Provide VHDL codes using Structural Modeling in this link: https://edaplayground.com/(a) use gate equivalence to convert the circuit into a four-level circuit containing only NAND gates and a minimum number of inverters. (Assume the inputs are available only in uncomplemented form.) (b) Take (a) and convert into a five-level circuit containing only NOR gates and a minimum number of inverters. (Assume the inputs are available only in uncomplemented form.)
- 5) Assume that the exclusive-OR gate has a propagation delay of 10 ns and that the AND or OR gates have a propagation delay of 5 ns. What is the total propagation delay time in the four-bit adder of the below circuit?Please written by computer source Question 1 a. Tri-state logic is often used in digital design to resolve the conflict that arises when more than one output is connected. With the aid of a diagram, explain how this can be used in a digital design to share a single bus. b. Examine the following VHDL statements and draw a synthesised schematic for the corresponding design. c. Using concurrent statements only, (no process), describe a decoder in VHDL which satisfies the following conditions, and draw the High level RTL schematic for this design. 3 inputs (A, B, C) and 1 output (Z). The output is equal to 1 when either input A is equal to 1 or only input C is equal to 1. All signals are of type 'std_logic d. VHDL allows the designer to describe hardware using different language constructs. Although, these constructs might have the same, or similar, functionality, the result of the synthesis is quite different. One example is the if-else and the case constructs. Explain the difference…Use VHDL to implement a 16-to-1 Multiplexer. The inputs are w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, and w11. The last four inputs are not attached to an input signal. How many select bits need the circuit?
- 3(a): Consider the following circuit, which uses two D flip-flops with falling edge triggers along with -bit full adder. The flip-flops are controlled by a single clock, C. Suppose C, Q0 and Q1 all initially have the value 0. First, fill in the blanks in the "i " = 0 (initial state)" row to show the values of D0 and D1 at this initial time (assume the results of the adder have had time to stabilize) . Next, show the values of Q0 , Q1, D0 , and D1 once they have stabilized after the ith falling edge of the clock, where i ranges from 1 to 4. Note that both the A and Carry In inputs of the adder are (Q not ) Q'0 not Q0 None of these first four rows should be the exactly the same.Solve the problem and simplify the output function using Quine – Mc Cluskey Methods. The following requirements must be met in solving the problem. Requirement:a. Truth Tableb. Timing Diagramc. Quine – Mc Cluskey Method d. Logic Diagram PROBLEM: F (A,B,C,D) = Σm (1,3,5,6,8,9,10,11,13,14)Implement the Boolean function: F(A,B,C,D)= Σm(0,2,3,7,8,10,12,15) using at most 5 pieces of 2x4 negative output, negative enable decoder and unlimited amount of any types of logic gates