Instruction 125-01 Shift 26 left 2 Add Jump address (31-0) 28 PC 431-28 RegDat Shin Jeft 2 Jump Branch MemRead Instruction 31-26] MemoReg Control A MemWrite ALUS RegWrite ALU Instruction (25-21] Read PC Read address register 1 Read Instruction [20-16 data1 Read Zero Instruction register 2 01-0 Read Instruction Instruction (15-11 memory Write Write data Registers ALU ALU register data 2 result Instruction[15-0 16 Sign- 32 extend ALU control Instruction (5-0 23x эм AddressRead data We Data data memory

Instruction 125-01 Shift 26 left 2 Add Jump address (31-0) 28 PC 431-28 RegDat Shin Jeft 2 Jump Branch MemRead Instruction 31-26] MemoReg Control A MemWrite ALUS RegWrite ALU Instruction (25-21] Read PC Read address register 1 Read Instruction [20-16 data1 Read Zero Instruction register 2 01-0 Read Instruction Instruction (15-11 memory Write Write data Registers ALU ALU register data 2 result Instruction[15-0 16 Sign- 32 extend ALU control Instruction (5-0 23x эм AddressRead data We Data data memory

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…
7-16. Add the following instructions to the computer of Sec 7-3 (EA is the effective address). Write the symbolic microprogram for each routine as in Table 7-2. (Note that AC must not change in value unless the instruction specifies a change in AC.) Symbol Opcode Symbolic Function Description AND 0100 AC ← AC ∧ M[EA] AND SUB 0101 AC ← AC - M[EA] Subtract ADM 0110 M[EA] ← M[EA] + AC Add to memory
int x = 0; co x = x + 3;|| x = x + 1; oc Command A = B + C is implemented with machine instructions; it is mapped to the atomic instruction TEMP = B + C; A = TEMP; where TEMP is the local process variable (so each process has its own). List all possible program traces and give the final value for each trace.
1. T/F - if (B)=006000 (PC)=003600 (X)=000090, for the machine instruction 0x032026, the target address is 003000.2. T/F – PC register stores the return address for subroutine jump.3. T/F – S register contains a variety of information such as condition code.4. T/F – INPUT WORD 1034 – This means Operating system should reserve 1034 bytes in memory5. T/F - In a two pass assembler, adding literals to literal table and address resolution of local symbol are done using first pass and second pass respectively.
Modify the following code to simulate a PEP/8 computer and instruction set for only the following instructions in the Image attached, to work in PEP/8 assembly language program : ORG $4000; start program ; start of program EQU MEMSIZE,$1000;size of memory ;Createing a structure to emulate the registers STRUCT Registers A RESW 1 ; register A X RESW 1 ; register X PC RESW 1 ; Program counter SP RESW 1 ; Stack pointer ENDS SECTION.BSS; declare variables REGS Registers; registers MEM RESW MEMSIZE; Memory array ENDSEC ORG $4000; start program LDX #$FF ; Initialize X to highest memory address STX REGS.SP; Set stack pointer to highest memory address CLRA ; clear A LDX #MEM; set X to point to the start of memory array LDAB #10 ; load the value 10 to B STAB 0,X ; Store 10 in first memory location LDX #MEM+2 ; Set X to point to third memory location LDAB #5 ; load 5 to B STAB 0,X ; store 5 in the third memory location LDX #MEM ; set X to point in the start of the array LDAA 0,X ; Load the…
Computer Science A[10] = x; Let x is saved in the register ($s0) and the base address of array A is saved in register ($s3). What is the equivalent MIPS instruction of this high-level language?
16. The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are a. AL=0FH; CF=1; SF=1 b. AL=F0H; CF=0; SF=0 c. AL=F1H; CF=1; SF=1 d. AL=1FH; CF=1; SF=1
A. Assume that the Instruction Pointer, EIP, contains 9610 and the assembly language representation of the instruction in memory at address 9610 is JB 175. If the flags are currently CF=0, ZF=0 and SF=1 what is the value of the EIP after the instruction executes? B. Assume that the Instruction Pointer, EIP, contains 15410 and the assembly language representation of the instruction in memory at address 15410 is JNS 189. If the flags are currently CF=1, ZF=0 and SF=1 what is the value of the EIP after the instruction executes? C. Assume that before the instruction is executed, the flags are CF=0, ZF=0 and SF=0 and the Registers have the values AL=0x35, BL=0x0F CL=0x25 and DL=0x78. What are the values of the flags after the instruction ADD AL,0x90 executes? D. The following instruction is executed. Assume that before execution, register R12 contains 0x85, R9 initially contains 0xC3, and the flags are ZF=0, SF=1, and CF=0. 0x indicates hexadecimal; do not include a 0x with your…
Q5. Given the content of memory and the registers below. i. Indicate the type of addressing mode of each line of instruction belowii. Deduce the target addressiii. Deduce the Value loaded into accumulator register (A) 10 marks Data at location Memory Address03600 3030103000 360000C303 6390003030 C303Memory content Base Register (B) 00600Program Counter (Pc) 003000Index Register (X) 000090 Register Content Instructions Opcodes - LDA = 00SN opcode n i x b p e Displacement Target Address (TA)1 000000 1 1 0 0 1 0 0110 0000 0000 2 000000 1 1 1 1 0 0 0011 0000 0000 3 000000 1 0 0 0 1 0 0000 0011 0000 4 000000 0 1 0 0 0 0 0000 0011 0000 5 000000 1 1 0 0 0 1 0000 1100 0011 0000 0011
Under the von Neumann architecture, a program and its dataare both stored in memory. It is therefore possible for a program,thinking that a memory location holds a piece of data when itactually holds a program instruction, to accidentally (or onpurpose) modify itself. What implications does this present to youas a programmer?
Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
Provide neat answers. Show all necessary steps. Translate the following code snippet written in C programming language into an instructionsequence written in MIPS Assembly language. You may assume that the values of the variables x,y, a, b, and c are in the general-purpose registers $s0, $s1, $s2, $s3, and $s4. if(x == y) {c = a - b;} else {c = b - a;}x = x + c;y--;