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nd the register that introduces the dependency. Highlight it if it is Load- nstruction that writes the register Instruction that reads the register beq x10, x11, exit li x10, 0

nd the register that introduces the dependency. Highlight it if it is Load- nstruction that writes the register Instruction that reads the register beq x10, x11, exit li x10, 0

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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a) Fill in the rest of the following table about the RAW data dependency between two instructions, and the register that introduces the dependency. Highlight it if it is Load-Use. The register Instruction that writes the register li x10, 0 Instruction that reads the register beq x10, x11, exit x10 3
Transcribed Image Text:a) Fill in the rest of the following table about the RAW data dependency between two instructions, and the register that introduces the dependency. Highlight it if it is Load-Use. The register Instruction that writes the register li x10, 0 Instruction that reads the register beq x10, x11, exit x10 3
3. Pipeline execution and RAW (Read-After-Write) data hazard and control hazards. The following high-level C code is translated to RISC-V assembly (a Midterm 2 question). Instructions are executed on the CPU using the standard 5-stage pipeline (IF, ID, EXE, MEM, and WB). Register files can be read/write in the same cycle, and instruction memory and data memory are separated. Branch outcome is determined at the end of ID stage. for (i=0; i!=n-2; i++) a[i] += a[i+1]; Variable n is stored in register x6 and i is in register x10. Array a is an array of integers (a word). # Initialize registers for variable i and n-2 li x10, 0 add x11, x6, -2 # i=0 # x11 now has n-2 # branch check loop: beq x10, x11, exit # if loop condition is NOT true, exit loop # load a[i] to register Iw x7, a(x10) # load a[i] to x7 # load a[i+1] to register addi x12, x10, 1 Iw x8, a(x12) # x12 now has i+1 # load a[i+1] to x8 # Do the addition of a[i] + a[i+1] and store the result to a[i] add x9, x7, x8 sw x9, a(x10) # a[i] + a[i+1], and in x9; # store a[i] + a[i+1] into a[i] # Increment loop index i and jump to the beginning of the loop addi x10, x10, 1 beq x0, x0, loop # i=i+1 # back to condition check # loop exit exit:
Transcribed Image Text:3. Pipeline execution and RAW (Read-After-Write) data hazard and control hazards. The following high-level C code is translated to RISC-V assembly (a Midterm 2 question). Instructions are executed on the CPU using the standard 5-stage pipeline (IF, ID, EXE, MEM, and WB). Register files can be read/write in the same cycle, and instruction memory and data memory are separated. Branch outcome is determined at the end of ID stage. for (i=0; i!=n-2; i++) a[i] += a[i+1]; Variable n is stored in register x6 and i is in register x10. Array a is an array of integers (a word). # Initialize registers for variable i and n-2 li x10, 0 add x11, x6, -2 # i=0 # x11 now has n-2 # branch check loop: beq x10, x11, exit # if loop condition is NOT true, exit loop # load a[i] to register Iw x7, a(x10) # load a[i] to x7 # load a[i+1] to register addi x12, x10, 1 Iw x8, a(x12) # x12 now has i+1 # load a[i+1] to x8 # Do the addition of a[i] + a[i+1] and store the result to a[i] add x9, x7, x8 sw x9, a(x10) # a[i] + a[i+1], and in x9; # store a[i] + a[i+1] into a[i] # Increment loop index i and jump to the beginning of the loop addi x10, x10, 1 beq x0, x0, loop # i=i+1 # back to condition check # loop exit exit:
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