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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Assuming that two processes are currently running; delaying execution before one of the processes completes. For the most part, you may consider the phase 1 is the most essential and the other is less important. The main memory can store just one action at a time. The CPU explains how it performs calculation on that? The choices of both include the stages involved in the functioning of a CPU?
- Assume a 3GHz processor executes three classes of instructions(A, B, C).i. Calculate the average CPI for this sequence of program.ii. Calculate the execution time for this sequence of program.iii. If we use a system with four same processors, there will bespeed up by a factor of 4 for classes A and C, but class B willremain unaffected. Calculate the new execution time for thissystem. What is the overall speed up? Class A B C CPI for class 4 2 10 IC in sequence 100 200 300a) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Suppose T1 does “Load X into register R1” machine instruction. Then the CPU scheduler switches the CPU to T2. Will T2 see the same vaue of R1 as loaded here by T1? (YES or NO)? Explain in less than 50 words. Be specific. (b) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Is it possible to have a moment (time instant) where both threads have made a request to Memory Unit to read some data (ex. as part of a “Load … into register …” instruction) and Memory Unit has not yet completed either of these two requests? Explain in less than 50 words.Assume two secondary memory processes exist. In light of phase 1, one priority is higher than the other. Only one process can fit in main memory. How does the CPU work on it? Can you explain the whole CPU mechanism?
- Because of this, the CPU suspends any currently executing processes until the interrupt has been resolved. Interrupt service is the term used to describe this. What is the rationale for halting the procedure that is presently in progress? Isn't it possible, as an alternative, to just finish the presently operating operation and deal with the interruption afterward?Question) In a microprocessor-based system with several tasks that are supposed to be executed more or less simultaneously, there is a necessary condition for the sum of the computing times of the tasks. Please state this. b) The upper limit contained in this condition is limited in practice to about 35% for real-time systems. Why is, in general, so much overhead necessary to be real-time capable? Please name the main culprit for this.NOTE: "Exekveringstid(ms)" means execution time or burst time in milliseconds Assume that a system with a CPU at one time has the following processes queued in the CPU's READY queue: Calculate the waiting time for the seven processes: 1) If FCFS is being used 2) If LRU is being used 3) If RR with time quantum of 8ms
- Asymmetric and symmetric multiprocessing are also possible. Can you explain the pros and cons of utilising many CPUs in a same program?Poll on the State of IT When both big-endian and little-endian CPU architectures are used in the same machine, interprocess communication breaks down. When can we anticipate seeing these issues resolved?