Outline of Chapter 4 Assignment This is general outline of the assignment. You have to watch all videos and read book sections accordingly. a) Definition of processor architecture with general diagram of processor. b) The Y8 Instruction Set Architecture i.Y8 Instructions and their byte level encoding ii. A comparison of RISC and CISC Instruction Set c) SEQ (Sequential Y86 processor) Hardware Structure

Outline of Chapter 4 Assignment This is general outline of the assignment. You have to watch all videos and read book sections accordingly. a) Definition of processor architecture with general diagram of processor. b) The Y8 Instruction Set Architecture i.Y8 Instructions and their byte level encoding ii. A comparison of RISC and CISC Instruction Set c) SEQ (Sequential Y86 processor) Hardware Structure

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Q1: Suppose the hypothetical processor has two I/O instructions: (3+3+3)0011=Load AC from I/O0111=Store AC to I/OIn this case, the 12-bit address identifies a particular external device. Show the program execution using figure for the following program:a) Load AC from device 6b) Add contents of memory location 880c) Store AC to device 7 (Note: Question is to be solved similar to the pictures attached with minimum explaination of a line or two with the steps and SHOULD include the memory location 880 as stated in the question)
I want all staps for Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “8” computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
21. a. Describe the basic format of an instruction, ensure to describe what each element in this format does. b. What are the RTN/Ls for the following MARIE instructions:a. Store Xb. Add Xc. Inputd. Halte. Skipcondf. Jump X c. Given the following memory values and a one-address machine with an accumulator: Word 10 contains 30 Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 What values do the following instructions load into the accumulator? a. Load IMMEDIATE 10 b. Load DIRECT 10c. Load INDIRECT 10 d. Load IMMEDIATE 20 e. Load DIRECT 20 f. Load INDIRECT 20
Question P .Implement and Compute the total memory traffic in bytes for both instruction fetch and instruction execution for the code that implements the expression a=(b*c) d on 3-, 2-, 1-, and 0- address machines. Assume opcode occupy one byte, address occupy two bytes and data values also occupy two bytes. The word length is one byte. Full explain this question and text typing work only We should answer our question within 2 hours takes more time then we will reduce Rating Dont ignore this line
Develop a hypothetical architecture with illustrative instruction and data formats, instruction sets, etc., explain the instruction and machine cycles step-by-step by developing a short program (at least, with two arithmetic operations, three logic operations, three memory or two L/C) operations) and by indicating the corresponding register operations. All architectural, etc., selections must to be justified sufficiently. CAN YOU EXPLAIN WITH THE EXAMPLE USING NUMBERS IN THE STACKS WITH EACH STEP INSTEAD OF PROGRAM.
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers (see image 1). Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage. If we have a simple scalar pipeline but allow out-of-order execution, we can construct the following table for the execution of the first seven instructions (see image 2). The entries under the four pipeline stages indicate the clock cycle at which each instruction begins each phase. In this program, the second ADD instruction (instruction 3) depends on the LOAD instruction (instruction 1) for one of its operands, r6. Because the LOAD instruction takes five clock cycles, and…
Can u please solve step by step ; clearly. Write the basic addressing modes of a CPU, and explain each one giving a simple instruction example.
I want all steps for Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “7” computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
In generall, computers think in terms of numbers (i.e. binary data). Thus, any operation performed in the computer must be done using either mathematical or logical operations. Given this inherit limitation of computers, what is the compare instruction actually doing when we, as assembly programmers, provide two numbers for it to "compare"? Furthermore, what assembly instruction is similar to the compare instruction? How are the two instructions different?
Add control states to the following to implement a two-word load constant value instruction, lv, such that lv $rd,1000000 yields rd=1000000. The constant value being loaded, 1000000 in this case, can be an arbitrary 32-bit value, thus it is the second word of the instruction. The first word of the instruction has the lv opcode and specifies rd. All MIPS instructions are just one word long, so there is no MIPS instruction like this and you will not find an explanation of it in the text, etc. You should use the encoding suggested by the when below, so an instruction like lv $5,42 would be encoded as the two-word sequence op(2)+rd(5), 42. when (op()) (op(2)) LvStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */Lv:
Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers (Image 1). Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage. If we have a simple scalar pipeline but allow out-of-order execution, we can construct the following table for the execution of the first seven instructions (Image 2). The entries under the four pipeline stages indicate the clock cycle at which each instruction begins each phase. In this program, the second ADD instruction (instruction 3) depends on the LOAD instruction (instruction 1) for one of its operands, r6. Because the LOAD instruction takes five clock cycles, and the…