Please consider the following segment of an assembly language program. Manually execute one instruction at a time and write the new resulting contents of conditions codes N/Z/V/C, Registers R5/R6, and New Memory Contents. Write the contents without any prefix or suffix, just the hex contents.
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- Assume the following register contents: $t0 = 0x01234567, $t1 = 0x56781234. Set back to these values back after answering each question. For the register values shown above, what is the value of registers ($t0, $t1, $t2, $t3) after executing each instruction? sll $t2, $t0, 2 and $t3, $t2, $t1Assume that registers $s0 and $s1 hold the values 0x90000000 and 0xA0000000, respectively. These are integer values. Please take into account that these are 32-bit registers. a) What is the value of $t0 after the following MIPS instruction has been completed? add $t0, $s0, $s1 $s0: 0 x 9 0 0 0 0 0 0 0 $s1: 0 x A 0 0 0 0 0 0 0Please answer this question and provide the explanation Assume the values of %ecx is 0x00000005 and %edx is 0x00000003. What would be the value of %ecx and %edx after performing the following instruction? 0x5555555461a <+0>: leal (%ecx, %edx, 8), %edx %ecx = 0x00000005, %edx = 0x0000003A %ecx = 0x00000005, %edx = 0x00000018 %ecx = 0x00000005, %edx = 0x00000030 %ecx = 0x00000005, %edx = 0x00000003 %ecx = 0x00000005, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x00000040 %ecx = 0x00000055, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x0000002A %ecx = 0x00000005, %edx = 0x00000025 %ecx = 0x00000005, %edx = 0x00000035
- For the MIPS assembly instructions below, what is the corresponding C statement?Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and$s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t1, $s1, 2add $t1, $t1, $s6lw $t1, 0($t1)sub $t0, $s3, $s4sll $t0, $t0, 2add $t0, $t0, $s7lw $t0, 0($t0)add $t1, $t1, $t0sll $t0, $s0, 2add $t0, $t0, $s7sw $t1, 0($t0)Assume that the state of the 8088’s registers and memory just prior to the executionof each instruction in problem 15 is as follows: * in photos*What result is produced in the destination operand by executing instructions (a)through (k)? *only b,c,e,g* b) ADC SI, AX(c) INC BYTE PTR [0100H] (e) SBB DL, [0200H] (g) NEG BYTE PTR [DI]+0010HFor all the questions in this assignment, you should use conditional execution of branch instructions only (i.e., do not use conditional execution of data processing instruction or other non-branch instructions). Question #1 . For each of the following C++-like pseudo code segments, write equivalent ARM assembly language instructions. if (r1 >= 10) { r2 = r2 - r1; } r2 = r2 + 60; if (r4 < 0) r4 = r4 + 100; else r4 = 100 - r4; if (r5 == r6) r5 = r5 + 80; else if (r5 < r6) r5 = r5 - 40; else if (r5 != r8) r5 = -r5; else r5 = 9*r5;
- What will be the values stored in registers r1 and r0 after the execution of the instruction mul r16, r17 if r16 and r17 originally contain the following values? (a) 0x58 and 0x37 (b) 0x29 and 0x496. Fill in the requested register values on the right side of the following instruction sequence:mov esi,OFFSET myBytesmov ax,[esi] ; a. AX =mov eax,DWORD PTR myWords ; b. EAX =mov esi,myPointermov ax,[esi+2] ; c. AX =mov ax,[esi+6] ; d. AX =mov ax,[esi-4] ; e. AX =Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?
- 19. The 8085 microprocessor respond to the presence of an interrupt a. As soon as the trap pin becomes ‘LOW’ b. By checking the trap pin for ‘high’ status at the end of each instruction fetch c. By checking the trap pin for ‘high’ status at the end of execution of each instruction d. By checking the trap pin for ‘high’ status at regular intervalsIn a register/memory type CPU, the instruction lengths are typically variable. This presents a problem when the program is incremented during the Fetch-Decode-Execute cycle. What statements(s) is/are NOT TRUE with regard to Program Counter (PC) incrementing? Select one or more A. The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be calculated. B . PC is incremented by the largest possible foxed value, irrespective of the variability of the instruction C. Increment value is known when the current instruction has completed execution. D. increment value is known when the current instruction is decoded with the Instruction Register (IR) E. PC incrementing method is implementation dependent. If R1 = 0xEF00DE12, R2 = 0x0456123F, R5 = 4, R6 = 28; Find the values of the destination registers for the following instruction? a) LSL R1, #8 b) ASR R1, R5 c) ROR R2, R6 d) LSR R2, #6 Substantiate your answers appropriately.