Q.2/ A- Using full-adder (block diagram), design a 2-bit parallel adder. B- Determine the outputs of the above adder for the following inputs. I. Ao A1 Bo B1
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- 1-Using the Karnaugh Method, design and draw the circuit of the logic circuit that gives the result of the multiplication of the two-bit numbers "AB" and "CD" according to minterms (SOP). Do not make any further simplifications before or after the Karnaugh Method. In tables and Karnaugh, ensure that the least significant bit is on the far right and the entries are sorted alphabetically. Make sure that the circuit you have drawn is understandable, the function you have written and the truth table are readable.Design a 3-bit counter that counts the following sequence: 7,5, 3. 1.0.7, 5. 3, 1, 0, 7. etc. Using the sequential design technique that starts from a state diagram, draw the state table. minimize the logic. and draw the final circuit. The outputs of logic circuit are 2 = Qo Q1. I, = Qo.Qi + Qo.Qi, Io = Qo.Q2, Cont2 = Qj Q2 Cont1 = Qu Q2. Cont0 = Q2 Qo.Q1. h = Qo.Qi + Qo.Q1, Io = Qo Qz Cont2 = Q, Q2 Contl = Qo Q2 Cont0 = Q2 Qo Qı Ij = Qo.Q, + Q».Qı, Io = Qo. Q2. Cont2 = Qj Q2. Contl = Qo.Q2. Cont) = Q2 L = Qo.Qı. I¡ = Q. Qj + Qu Q Io = Qv.Qz Comt2 = Q, Q, Contl = Q Q2 Cont0 = Q2 !! fefsto How much will be per-product cost and thDesign a 4-bit arithmetic circuit, with two selection variables S1 and S0, that generates the arithmetic operations in the following table. Draw the logic diagram for a single bit stage. Note that B’ represents “Not B”. Draw the logic diagram for a single bit stag
- If a fault occurs in connections C5 (stuck-at-1) for the following logic circuit, the appropriate fault-test by using Boolean difference technique .......... C1 X1 Cs C2 X2 Cs C6 C10 C9 C7 t0 t2 t3 t1 OLogic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)Using full adders in block diagram, other needed logic gates. Show the design of a circuit that performs A – B based on using 2's complement arithmetic where A and B are two unsigned 4-bit numbers. State the condition for error in your design.
- An X-input exclusive-OR gate and a Y-input exclusive-OR gate (where X=3, Y=4 have their outputs connected to a 2-input exclusive-NORgate. Do the following:a) Draw the logic diagram and analyze the logic expression of the output (in standard SOPform).b) List out all essential prime implicants.1. Gray code to Binary converter: Gray code is one of the codes used in digital systems. It has the advantage over binary numbers that only one bit in the code word changes when going from one number to the next. (See Table 1). Design a combinational circuit with 4 inputs and 4 outputs that converts a four- bit gray code number into an equivalent four-bit Binary number. Use Karnaugh map technique for simplification. Use LogicWorks for pre-lab demonstrations. Select the library "7400dev.clf* in the Parts Palette and then select the XOR chip 74-86. This would give you a set of 4 XOR's as shown in Fig. 1, just like the hardware chip 74-86. You could use as many as needed from these XOR gates in your design. Get back to ALL LIBRARIES and select switches for the inputs and Binary Probes as indicators of the outputs. Verify your design in the pre-Lab. During the Lab construct the circuit and verify its operations.Draw a simplified Logic Circuit Diagram by implementing Full Adder in product of sums
- a) Create a 4 Variable Karnaugh Map in paper by mapping 1’s for given standard SOP Boolean expression. After mapping , make relevant groups within Karnaugh Map by considering rules for making groups for 4 variable Karnaugh Map. After making relevant grouping , extract the minimum SOP expression by considering rules for extracting minimum SOP using Karnaugh Map. * Standard SOP: *Create Circuit Diagram using logic gates and logic converter in Multisim for given standard SOP and minimum SOP which you have solved. Do make sure that truth table for both expressions should evaluate same result.a) For the given logic circuit diagram write the program by using the gate level modeling. b) For the given truth table write the program by using the data flow Modelling. c) Write the test bench of the given logic circuit with all possibilities Y1 Y2 Y3 Y4 Y5 Y6 Y7 A2 A1 A0Draw the equivalent logic circuit diagram of the following expressions : a. XY = F b. X + Y = F XÝZ = F c. d. XY + XZ = F e. XYZ + XÝZ = F