Q11/To design a counter which count in the following sequence 7,6,3,5,0,1 by using SR- F.F, the * input of SR-F.Fs are SA=AB'C'+BC, RA= BC+AB'C, SB=AB'C, RB=A'BC, SC=AB'+A'C'+B'C,RC= AC' SA=AB'C', RA= C'+AB' , SB=A'C, RB=A'B, SC=B'+C',RC= BC SA=AB'C'+A'B, RA= C'+AB'C, SB=AB'C', RB=A'B, SC=B'C'+B, RC= AB None of them O SA=A'B'C+A'BC, RA= AB'+BC ,SB=AB'C, RB=A'BC, SC=A'+AB', RC= AC'

Q11/To design a counter which count in the following sequence 7,6,3,5,0,1 by using SR- F.F, the * input of SR-F.Fs are SA=AB'C'+BC, RA= BC+AB'C, SB=AB'C, RB=A'BC, SC=AB'+A'C'+B'C,RC= AC' SA=AB'C', RA= C'+AB' , SB=A'C, RB=A'B, SC=B'+C',RC= BC SA=AB'C'+A'B, RA= C'+AB'C, SB=AB'C', RB=A'B, SC=B'C'+B, RC= AB None of them O SA=A'B'C+A'BC, RA= AB'+BC ,SB=AB'C, RB=A'BC, SC=A'+AB', RC= AC'

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Please help with the following in regards to Nand2Tetris, and hack code, so hack assembly and hack vm. There can be more that one answer to a question if so please explain why. 1d. A symbol may be: a. @followed by a number b. @followed by a lower case word c. @followed by upper case word d. a and b e. b and c 1e. Every boolean expression of N inputs and one output can be implemented a. using a combination of D flip-flops, multiplexors and registers. b. by connecting the output directly to all of the N inputs. c. using a combination of And and Or gates. d. using a combination of And, Or and Nand gates 1f. In twos-complement arithmetic, to create a negative value of a number X: To subtract X from Y: a. invert (Not) every bit in the number X. b. invert the most significant bit of X. c. add 1 to X, and invert every bit. d. subtract 1 from X, and invert every bit e. add 1 to X f. invert every bit of X and add 1
A Gray code is a sequence of binary numbers with the property that no more than 1 bit changes in going from one element of the sequence to another. For example, here is a 3-bit binary Gray code: 000, 001, 011, 010, 110, 111, 101, and 100. Using three D flip-flops and a PLA, construct a 3-bit Gray code counter that has two inputs: reset, which sets the counter to 000, and inc, which makes the counter go to the next value in the sequence. Note that the code is cyclic, so that the value after 100 in the sequence is 000.
Build a circuit that takes four bits as input: W, X, Y, Z. Treat WX as a 2-bit unsigned binary number, and treat YZ as a second 2-bit unsigned binary number. Your circuit should generate the output corresponding to the product of WX and YZ. You will need 4 bits of output for this problem.For example, if your input was 1011, your inputs correspond to 2 and 3. That product is 6, so your output will be 0110.Create a truth table for this problem, show all k-maps and minimizations, and build the corresponding (minimized) circuit. Use XOR, XNOR, NAND, and NOR as appropriate if it reduces the number of gates used.
Design a Moore FSM for a Sequence Derector that detects five consecutive bits of "zero" in the input stream of bits, labeled x. The output z equals 1 if, during five consecutive clock cycles, the input x was equal to "zero". Once the sequence is detected, the FSM returns to the initial state S0. Add an asynchronous reset, active low, to the FSM.
Write a C++ program that calculates the XOR gate of binary, use the XOR() – a function that performs bitwise operation XOR Sample Output Enter First Number: 10111 Enter Second Number:11111 THE RESULT IS: 1000
Design a circuit that takes three bits, X2, X1, X0 as input and produces one output, F. F is 1 if and only if 2<=X<=5 when X = (X2, X1, X0) is read as an unsigned integer. For example, if X2=1, X1=0, and X0=0, then the unsigned binary value is 100, which is 4, so the output would be 1. Your Assignment For This Problem Includes the Following Design the necessary circuit using Logisim to implement the situation described above. Use Kmaps for simplification. Be VERY careful to get the correct functions for your output before simplifying and designing the circuit with Logisim. You should minimize the circuit. Your circuit should have three inputs and one LED output. All inputs (X2, X1, X0) and output (F) should be labeled (in Logisim, not by hand). Please use these names to indicate the inputs and output so all projects are consistent. You should also include your name as a label on the circuit. Test your circuit to be sure it is working correctly.
MODIFY THIS VERILOG CODE. THE OUTPUT OF THE QA,QB & QC (that will be seen on gtkwave) SHOULD BE:qa qb qc 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 1 module finals_nake(in, clk, qa, qb, qc); input in, clk; output qa, qb, qc; wire ja, jb, jc, ka, kb, kc; // Negated inputs wire in_n, clk_n; assign in_n = ~in; assign clk_n = ~clk; // JK equations based on provided equations assign ja = (qb & ~qc & ~in) | (qb & qc & in); assign ka = clk & clk; assign jb = (~qa & ~qc & ~in) | (~qa & qc & in); assign kb = qa | (~qc & ~in) | (qc & in); assign jc = (~qc & ~in) | (~qc & in); assign kc = clk & clk; //jka wire jka1, jka2, jka3, jka4; assign jka1 = ~(jka4 & ja); assign jka2 = ~(jka3 & ka); assign jka3 = ~(jka1 & jka4); assign jka4 = ~(jka2 & jka3); assign qa = jka3; //jkb wire jkb1, jkb2, jkb3, jkb4; assign jkb1 = ~(jkb4 & jb); assign jkb2 = ~(jkb3 & kb); assign…
Write the word TRUE if the statement is correct If the statement is false, replace the word's that, if substituted for the underlined word/s, would make the statement correct. Flip-flops are asynchronous bi-stable devices because there can only be two states. Negative edged triggered flip-flop has a bubble on the clock input signal which means that the circuit will only respond to negative The S-R flip-flop is a single-input version of the J-K flip-flop formed by tying both inputs together
Using the truth table below ( An example sum-of-products expression is (A+B+C)(A+B+C')(A+B'+C)(A'+B+C).) a. Write a product-of-sums Boolean expression bexp4 for the output ? of the truth table b. Draw a circuit that is a direct translation of bexp4 without any simplification. For the circuit, use a layout that is analogous to the layout of the sample circuit below (where the and and or gates are appropriately swapped).
Design a state machine to output the binary values (include leading zeros e.g. 0101} for the following sequence each time a increase count input line changes from 0 to 1. When it reaches the end it starts over at beginning {1, 3, 9, 5, 7, 3}. It has a second input line forward/reverse which will change its direction to go in reverse direction if this line is high..
Write a C++ program that gives the outputs of this ./a.out -c ATTCGG6 22 240 ./a.out -c CAT3 132 ./a.out -d 6 22 240ATTCGG ./a.out -d 3 132CAT
Implement a 4-bit counter that counts down, starting at fifteen and ending at zero. Also, implement a reset that allows you to place it in its initial value which would be 15. For this make use of FF JK and logic gates.