Q2\ Consider a pipeline CPU architecture that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Assume CPI = 1 1. Suppose that the cycle time of this pipeline without forwarding is 100 ps. Suppose also that adding forwarding hardware will reduce the number of NOPs from 0.4*n to 0.1*n, but increase the cycle time to 125 ps. What is the speed up of this new pipeline compared to the one without forwarding? How many NOPs (as a percentage of code instructions) can remain in the typical program before that program runs slower on the pipeline with forwarding? 3. Rearrange and Insert NOPs to ensure correct and efficient execution (Assuming 5 stages pipeline) for following assembly language: ADD R5, R2, R1 AND R2, R5, R2 STR RS, [R2, #4] LDR R6, [R4, #0] OR BE BE 01

Q2\ Consider a pipeline CPU architecture that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Assume CPI = 1 1. Suppose that the cycle time of this pipeline without forwarding is 100 ps. Suppose also that adding forwarding hardware will reduce the number of NOPs from 0.4n to 0.1n, but increase the cycle time to 125 ps. What is the speed up of this new pipeline compared to the one without forwarding? How many NOPs (as a percentage of code instructions) can remain in the typical program before that program runs slower on the pipeline with forwarding? 3. Rearrange and Insert NOPs to ensure correct and efficient execution (Assuming 5 stages pipeline) for following assembly language: ADD R5, R2, R1 AND R2, R5, R2 STR RS, [R2, #4] LDR R6, [R4, #0] OR BE BE 01

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Let's assume that there are three processors, Pa, Pb, and Pc, like below. You can assume 1-way superscalar, no hyper-threading, and no pipelined for all processors. Pa: 4 GHz clock rate, CPI: 2.2 Pb: 3 GHz clock rate, CPI: 1.5 Pc: 2.5GHz clock rate, CPI: 1.05.1. Show each processors' performance in terms of instruction per second.
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In the examination of how data dependences affect execution in the basic 5-stage pipeline, this exercise refers to the following sequence of instructions: or r1,r2,r3 or r2,r1,r4 or r1,r1,r2 Also, assume the following cycle times for each of the options related to forwarding: Assume there is no forwarding in this pipelined processor. Indicate hazards and add nop instructions to eliminate them. Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them. What is the total execution time of this instruction sequence without forwarding and with full forwarding?