Q2. Identify types of addressing modes used following. Intruction 1. MOV -2[BX], AX 2. MOV CX, [BX+2] 3. ADD AX, ARRAY1[BX] 4. MOV TEMP, 10H 5. MOV BX, 2+[SI]
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A: Step by step explanation is in given below.
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Q: addressing modes
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Q: Q2. Identify types of addressing modes use following. Intruction 1. MOV -2[BX], AX 2. MOV CX, [BX+2]…
A: Basically addressing modes is the way in which the operand of an instruction is specified.
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- Fill in blank Suppose that linear page table is used where the memory addresses are 12-bit binary numbers and the page size is 256 bytes. If a virtual address in binary format is 101000011100, then the VPN (virtual page number) in binary format will be ---------please sol Q2) Given a physical memory of 8 k and a cache memory of 512 bytes with block size 64 bytes. Thesystem uses associative mapping with set size 2 lines per setA- How the memory address will be split to indicate tag, and offsetB- What is the size of tag directory.Determine the number of page table entries (PTEs) that areneeded for the following combinations of virtual address size(n) and page size (P):
- Can you describe the challenges involved in developing a cache replacement strategy that is compatible with any and all address sequences?Mapping from high level addresses to low level addresses is known as address resolution. True or False?What is the difference between using direct and indirect addressing? Give an example.
- A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words.i) How many bits are there in the tag, index, block and word fields of the address format?ii) How many bits are there in each word of cache, and how are they divided into functions? Include a valid bit.iii) How many blocks can the cache accommodate?Describe the problems encountered while trying to build a cache replacement technique that is optimal for all addresses.. Fully AssociativeParameters• Main Memory: 2 GB• Block/Line Size: 32 B• Cache: 1 MB Fully AssociativeQuestions• How many main memory blocks are there?• How many cache lines are there?• How many memory blocks map to a single cache line?• What is the address breakdown for RAM?Block Index Byte Offset• What is the address breakdown for cache?Tag Byte Offset• Lookup Algorithm for Address X:
- Explain why IN/OUT (port-based) accesses provide lower I/O performance than MMIO. Select all correct answers. Note - select only answers that cause IN/OUT accesses to be slower than MMIO. You may assume that the instruction does not result in crossing a page boundary. a.Overhead incurred due to bus locking b.Overhead incurred due to the need to do page table walks c.Overhead due to instruction emulation d.Overhead due to page faults (#PF) e.Overhead due to 8 byte limit on I/Os f.None of the aboveconsider someone is using direct-mapped cache memory, each external memory address maps to what? a specific cache memory location one of many different cache memory locations a unique cache memory location, not shared with other external addresses a randomly-selected cache memory locationplease sol Q1) Given a memory of 16k and a cache memory of 1024 bytes with block size 128 bytes. Thesystem uses Direct mapping.A- How many blocks available in both physical memory and cache memory B- How the address will be split to indicate tag, line (block no) and offsetC- Calculate the cache line number and offset in cache that will contain the content ofmemory address 230.