Que. When the R/W bit of the status register of the DMA controller is set to 1. i) Read operation is performed ii) Write operation is performed iii) Read & Write operation is performed iv) None of the mentioned

Que. When the R/W bit of the status register of the DMA controller is set to 1. i) Read operation is performed ii) Write operation is performed iii) Read & Write operation is performed iv) None of the mentioned

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 11VE

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Que. When the R/W bit of the status register of the DMA controller is set to 1.

i) Read operation is performed

ii) Write operation is performed

iii) Read & Write operation is performed

iv) None of the mentioned

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