RD* = 0 for a memory read bus operation. True False
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- please explain step by step how to calculate the number of transistors given the logic gates AND, OR, NOT.(b)How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?Q: Show, how to use the ROM circuits to multiply two binary numbers each of two bits.(DSD)
- Draw the block diagram for a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.Consider two microprocessors having 8-bit and 16-bit wide external data buses, respectfully. The two processors are identical otherwise and their bus cycles are the same speed. Suppose all instructions and operands are two Bytes. By what factor do the maximum data transfer rates vary? Suppose all instructions and operands are one Byte. By what factor do the maximum data transfer rates vary? Discuss your answers.5 (b) How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates? Provide the circuit as well.
- Draw the implementation of decoding of binary state 5, and binary state 3 for a 3- bit synchronous binary counter. Show the entire timing diagram and the output waveforms of the decoding gates.What is the vhdl code for 4 bit parallel in parallel out register using d flip flop using logic gates(and ,or,...)?answer: If a memory of 0.5K bytes is connected to 8085 MP, Then the number of lower order address lines required are -------lines, and if 2 higher order address lines are considered as don't care lines,then a fold back space is exists and equals .to----bytes