Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second).This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operandstore unit. The instruction set includes simple instructions with the following timings:SET reg, immed; 3 clock cyclesLOAD reg, mem ; 4 clock cyclesADD reg, reg ; 3 clock cyclesADD reg, immed; 2 clock cyclesLOOP LabelName ; 8 clock cyclesAssume that the following code fragment is used to sum the element of a numeric array.SET reg1, 0;initialize sumSET reg2, MAX_SIZE ;initialize loop counterSET reg3, @list ;initialize array pointerProcessArray:LOAD reg4, [reg3] ;fetch current list elementADD reg1, reg4 ;add current list elementADD reg3, 4;move array pointer to next elementLOOPProcessArray ;auto-decrement reg2, jump to more if reg2 # 0If the initialization code has already executed (i.e. the SET instructions have already finished execution)how many array elements can be processed in 4.4 milliseconds (ms)? Round your answer to the nearestinteger. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations,implying that the array can be as large as desired.

Name: Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second).This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operandstore unit. The instruction set includes

Engineering

Computer Science

Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, immed ; 3 clock cycles

Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, immed ; 3 clock cycles

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word ofmemory.a. How many bits are needed for the opcode?b. How many bits are left for the address part of the instruction?c. What is the maximum allowable size for memory?d. What is the largest unsigned binary number that can be accommodated in one word of memory?
A computer with a 32-bit word uses an instruction format that includes direct and indirect addressing of 8 megabytes and one of 16 registers. The highest order bits are used for the opcode, followed by the bits indicating the register, followed by the indirect/direct bit, followed by the bits indicating the memory address. Draw the instruction word's format, showing how many bits are used for all four fields (Make sure to show here how many bits for each and the order in which they appear. You can submit a drawing of the word's format separately
Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. How many bits can be used for the memory address?
A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.Q.) What is the maximum allowable size for memory?
A computer with a 32 bit word uses an instruction format that includes direct and indirect addressing of 8 megabytes and on of 16 registers. The highest order bits are used for the opcode, followed by the bits indicating the register, followed by indirect/direct bit, followed by the bits indicating memory address Draw the instruction word's format, showing how many bits are used for all four fields
Suppose r0 = ox300010A0, r2 = 0x00000011, and the memory layout is as follows Address: Data: 0x300010A7 0x72 0x300010A6 0XA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0XA5 0x300010A0 0x01 -What are the values of r0 and r1 after executing the following code? Illustrate your process in a memory map. LDR r1, [r0], #3 ADD r1, r1, r2 STR r1, [r0, r#4]
Suppose r0 = ox300010A0, r2 = 0x00000011, and the memory layout is as follows Address: Data: 0x300010A7 0x72 0x300010A6 0XA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0XA5 0x300010A0 0x01 -What is the Value of r0 and r1 after executing LDR r1, [r0, #2] -What are the values of r0 and r1 after executing the following code? Illustrate your process in a memory map. LDR r1, [r0], #3 ADD r1, r1, r2 STR r1, [r0, r#4]
A Digital computer has a memory unit with 32 bits per word (memory element). The instruction set consists of 260 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. bits. How many bits are needed for the opcode? bits How many bits are left for the address part of the instruction? MBytes What is the maximum allowable size for memory (in MegaBytes) that can be accessed directly?
A general register, a single accumulator, or a stack are the three potential configurations that might be chosen for the central processing unit (CPU) of a computer. The stack is the most common of these three options. Each choice comes with its own individual combination of benefits and drawbacks. It is up to you to provide a response, and the response that you provide may be accurate or it may be erroneous.
The assembly language instruction ADDA 0x01FE,i is language: (put one space between bytes if the instruction is not unary) when converted into hexadecimal machine
Part 2: Status Flags There are more registers inside of the CPU that we don't have direct access to. One of these is the EFLAGS register. This register holds the values of the flags used in the CPU's operation. Flags are just single bit values that represent the state of the processor - usually 1 means a setting is on or true, and 0 means it is off or false. If a flag has the value 1, we say the flag is set. If it has the value 0, we say it is clear. "Setting" a flag means setting it's value to 1, and "clearing" a flag means setting its value to 0. The status flags are flags that show the outcomes of certain operations. These can be used to check the state of the computations and react accordingly. For example, the carry flag is set if the result of an unsigned addition is too large to fit into the same space as the numbers used during the addition. Look at the following addition operation: 11111111 + 00000001 = 100000000 Note that the result of the addition is 9 bits long, even…
Suppose that you are working with a CISC machine using a 1.6 GHz clock (i.e., the clock ticks 1.6 billion times per second). This particular computer uses MASM-like instructions with the following timings: ADD reg, mem ADD reg, immed LOOP _LabelName ; 8 clock cycles (i.e., the ADD micro-program has 8 instructions) ; 3 сlоck суcles 7 clock суcles Suppose that the following code fragment is used to sum elements of a numeric array. For this problem, assume that memory limitations are non-existent and that there is no limit to the size of the array. MOV MOV MOV BX, 0 ЕСХ, МАХ_SIZE ESI, OFFSET list ;initialize array pointer ;initialize sum ;initialize LOOP counter _ProcessArray: ADD ADD LOOP ProcessArray ВХ, [ESI] ESI, 2 ;Add current list element ;Move array pointer to next element ;auto-decrement ECX, jump to more if ECX = 0 After initialization, how many array elements can be processed in 2.8 millisecond (ms)? Round your answer to the nearest integer. Note that 1 ms = 0.001 second.