Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% B 2 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles
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- Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ CFollow this steps. Have to Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.Please,Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.
- Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?Consider two different implementations, P1 and P2, of the same instruction setarchitecture. There are four classes of instructions (A, B, C, and D).P1 has a clock rate of 1.5 GHz and CPI for each instruction class is as follows:Class CPI for this classA 1B 2C 3D 4P2 has a clock rate of 2.0 GHz and CPI for each instruction class is as follows:Class CPI for this classA 2B 2C 2D 2a. Given a program with 106 instructions divided into classes as follows: 10% classA, 20% class B, 50% class C and 20% class D, which implementation is faster?Give downvote if plagiarized or from internet A program is run on a system with two types of machine language instructions: type A instructions each require 3 clock cycles, while type B instructions each require 1 clock cycle. If 100 million type A instructions and 400 million type B instructions are executed, what is the CPI for this program? A program is run on a system with two types of machine language instructions: type A instructions each require 3 clock cycles, while type B instructions each require 1 clock cycle. If 100 million type A instructions and 400 million type B instructions are executed, what is the CPI for this program?
- Consider a program that declares global integer variables x, y[10]. Thesevariables are allocated starting at a base address of decimal 1000. All thesevariables have been initialized to zero. The base address 1000 has been placed in$gp. The program executes the following assembly instructions:lw $s1, 0($gp)addi $s1, $s1, 25sw $s1, 0($gp)lw $s2, 12($gp)add $s2, $s2, $s1sw $s2, 8($gp)sw $s2, 12($gp) What are the memory addresses of variables x, y[0], and y[1]? What are the values of variables x, y[0], y[1], and y[2] at the endof the program?Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?Convert the given code fragment to assembly code fragment, using only instructions of the following types. These instructions are generally discussed in class. Here X,Y,Z are any memory locations; R, R1, R2 are any general registers; L is a label in the code (you can use any names as labels, ex. L, L1, L2 etc. ). load X, R //copy contents of memory location X into R. store R, X //Store contents of R into Mem location X cmp R1, R2 //Compute R1-R2 and update condition codes; //throw away result of subtraction. jmp L //Jump to location L in the code. jmpp L //If P bit is 1, Jump to location L in the code add X, R //Add contents of X,R and store result in R; //Also update the condition codes. Be careful about what type of argument is allowed in the instruction (Memory or Register). Ex. the first argument of ADD instruction is memory, not register. Do Not…
- Consider a generic processor executing the following set of machine instructions. Memory location 34 contains a value 20. What statement best express the final outcome? MOV R1, #0 MOV R2, #34 MOV R3, #1034 ADD R1, (R2) MOV (R3), R1 Select one or more A. memory location 20 contains value 1034 B.memory location 1034 contains value 54 C. memory location 1034 contains value 34 D. memory location 20 contains value 34 E. memory location 1034 contains value 20CODE IN JAVA !!!!!!!!!!!!!!!!!!!!!!! Provide a code for LRU The Last Recently Used (LRU) solution for the memory page replacement but using two bits (boolean variable in Java) for the clock algorithm with one indicates the reference bit and the other indicates the read/write bit. Here we assume for all the processes, the pages with the number 2 and 5 involve data writing operation; all the other numbers (1, 3, 4, 6) only involve reading operations. Provide output examples of the code at the bottom.Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.