Suppose we have the instr Memory 100 600 R1| ... 400 300 ... 500 100 600 500 ... 700 800 Assume R1 is implied in t in the following addressir a) Immediate addres b) Direct addressing c) Indirect addressin d) Indexed addressin
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- Most Intel CPUs use the __________, in which each memory address is represented by two integers.If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Suppose we have the instruction Load 0000. Given memory and register R1 contain thevalues below:R130Memory Address Content0000 40...0010 30...0020 78...0030 55...0040 77...0050 84 Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator using the following addressing modes: a. Immediateb. Directc. Indirectd. Indexed
- Assume that registers $s0 and $s1 hold the values 0x90000000 and 0xA0000000, respectively. These are integer values. Please take into account that these are 32-bit registers. a) What is the value of $t0 after the following MIPS instruction has been completed? add $t0, $s0, $s1 $s0: 0 x 9 0 0 0 0 0 0 0 $s1: 0 x A 0 0 0 0 0 0 06. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…1. Name all of the general purpose registers and some of their special functions. 2. How are the segment registers used to form a 20-bit address? 3. (a) If CS contains 03E0H and IP contains 1F20H, from what address is the next instruction fetched? (b) If SS contains 0400H and SP contains 3FFEH, where is the top of the stack located? (c) If a data segment deigns at address 24000H, what is the address of the last location in the segment? 4. Explain what the instruction array and data caches are used for. 5. What is the EU and BIU, and what purpose in the microcomputer? 6. Two memory locations, beginning at address 3000H, contain the bytes 34H and 12H. What is the word stored at location 3000H? See Figure 2.26 for details. Address 3000 Data 34 3001 12 Figure 2.26 For question 6 7. What is a physical address? What are the differences between the 8086 logical and physical memory maps? 8. May memory segments overlap? If so, what is the minimum number of overlapped bytes…
- Suppose we have the instruction Load 1000. Given memory and register R1 contain the values below: Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below:Assume the register ($s1) contains (0x12345678). Write at most two instructions to move ONLY the fourth byte value in the register ($s1) into the data memory at address stored in ($s0). Hint: In this problem, the fourth byte value in the register ($s1) = "0x12"The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=800 T1=200 T2=200 T3=300
- The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction.The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Immediate Mode Direct Mode Register Relative Mode Index ModeNote: Choose your own values for variables k – w, T1, T2. Choose any one of the given value for T3 (200 or 300).1) For a Pentium II descriptor that contains a base address of 0004B100H, a limit of 00FFFH, and G = 1, what starting and ending locations are addressed by this descriptor? 2) Code a descriptor that describes a memory segment that begins at location 0005CF00h and ends at location 00060EFFh. The memory segment is a data segment that grows upward in the memory system and can be written. The segment has a user level privilege (lowest) and has not been accessed. The descriptor is for an 80386 microprocessor.Consider a 16-bit processor in which the following appears in the main memory, starting at location 200.a. The first part of the first word (content at 200) indicates that this instruction loads a value into an accumulator; the value of 300 in location 201 may be part of the address calculator. The mode field specifies an addressing mode and, if appropriate, indicates a source register. a. Assume that when used, the source register R1, which has a value of 500. b. There is also a base register that contains the value 100, Assume that location 249 contains the value 399, location 250 contains the value 400, and so on. Determine the effective address and the operand to be loaded for the following address modes: