cycles each, and the remaining 25 instructionstake 1 clock cycle each. Assume that there aremstruction pipeline of RIS C processor17heTheFetchfollowvingTastruction7hasstagesDecode (ID)Operand FetchyCIF) Instruction(OF). Perform Operation (PO) and WritebackWB). The IF, ID, OF and WB stages tak e lclockcycleeachforeveryinstruction.Considersequence of l 00 instructions.InatheΡΟstage,instructions take 3clock40cycleseach,35instructionstake2clockcycles each, and the remaining 25 instructionstake 1 clock cycle each. Assume that there areno data hazards and no control hazards.Thenumberof clock cycles requiredforcompletion of execution of the sequence o1instructions is

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Description: cycles each, and the remaining 25 instructionstake 1 clock cycle each. Assume that there aremstruction pipeline of RIS C processor17heTheFetchfollowvingTastruction7hasstagesDecode (ID)Operand FetchyCIF) Instruction(OF). Perform Operation (PO) and Wr

The answer for the given question is 219.The explanation is as follows.

Engineering

Computer Science

The instruction pipeline of a RISC pr Tnstruction Fetch 7os 1350 following stnges E), Instruction De code (ID) Otperand Fetch Perform Operation ( PO) and Writeback 1. (OF). (WB). The IF, ID. CF and WB stages take clock cycle each for every instruction. Consider instructions. In sequence of 100 a the PO stage, 40 instructions take 3 clock сусles each, 35 instructions take clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence ol instructions is

The instruction pipeline of a RISC pr Tnstruction Fetch 7os 1350 following stnges E), Instruction De code (ID) Otperand Fetch Perform Operation ( PO) and Writeback 1. (OF). (WB). The IF, ID. CF and WB stages take clock cycle each for every instruction. Consider instructions. In sequence of 100 a the PO stage, 40 instructions take 3 clock сусles each, 35 instructions take clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence ol instructions is

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Two computers have 8-stage fetch-execute cycles where branches are determined in stage 4.One computer is not pipelined, and the other is pipelined. Assuming that tp = 1, answer thefollowing questions when running a program with 50,000 instructions where 4,000 of theinstructions are conditional branches and each branch, if taken, skips over 5 instructions.a. How much faster is the pipelined machine over the non-pipelined machine assumingthat no branches are taken.b. How much faster is the pipelined machine over the non-pipelined machine assumingthat all branches are taken?
Assuming that memory takes 4 cycles after MEMread to complete the read, how many clock cycles does it take to fetch and execute one MIPS addi instruction using: when (op()) {addi} AddiStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */Addi: SELrs, REGout, Yin IRimmedout, ALUadd, Zin Zout, SELrt, REGin, JUMP(Start) You may use the simulator to help you answer this question.
Assume a 5-stage pipelined CPU (IF – ID – MU– EX – WR) requires following time for differentsections: Pipeline stages ----Required time Fetch Unit ---15 nsDecode Unit ---10 nsMemory Unit---- 20 nsExecution Unit---- 8 nsWrite back Unit ----15 ns The maximum delay required to transfer contents from one state to another is 2ns.a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume thatInstruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions:7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU readonly one data from RAM or save only one data to RAM at a time. Calculate the execution timefor the first 10 instructions of a program as well. Assume the condition is evaluated TRUE.
Assume for a given program, 60% of the executed instructionsare of Class A, 10% are of Class B, and 30% are of Class C. Furthermore,assume that an instruction in Class A requires 3 cycles, an instruction inClass B requires 2 cycles, and an instruction in Class C requires 2 tocomplete. i. Compute the overall CPI for this program.ii. Compute the clock rate of the CPU when the time it takes tocomplete 20 instructions is 1.73 ???????????
Very urgently needed!! Suppose before the CALL instruction within a code the registers hasfollowing data:SS=1E00H, SP=000AH, CS=85D9H, IP=10B5H, AX =1D02H, CX=04A8Hand DX=6550H.Draw a schematic diagram to illustrate what will happen after the CALLinstruction executes. Note that CALL instruction also stores the value ofregisters AX, DX and CX into the stack segment as they are being used inthe called procedure.
Q. What is the baseline performance (in cycles, per loop iteration) of the code sequence in if no new instruction’s execution could be initiated until the previous instruction’s execution had completed? Ignore front-end fetch and decode. Assume for now that execution does not stall for lack of the next instruction, but only one instruction/cycle can be issued. Assume the branch is taken, and that there is a one-cycle branch delay slot. Latencies beyond single cycle: Latencies beyond single cycle:Memory LD +6Memory SD +4Integer ADD, SUB +1Branches +2fadd.d +4fmul.d +6fdiv.d +10Execution codeLoop : fld f2, 0(Rx)I0: fdiv.d f8, f2, f0I1: fmul.d f2, f6, f2I2: fld f4, 0(Ry)I3: fadd.d f4, f0, f4I4: fadd.d f10, f8, f4I5: fsd f10, 0(Ry)I6: addi Rx, Ry, 8I7: addi Ry, Ry, 8I8: sub x20, x4, RxI9: bnz x20, Loop Q. Think about what latency numbers really mean—they indicate the number of cycles a given function requires to produce its output. If the overall pipeline stalls for the latency cycles of…
Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this case
Modiflow y the beprogram given to include response time program;FCFS CPU SCHEDULING ALGORITHM #include<stdio.h>#include<conio.h>main(){int bt[20], wt[20], tat[20], i, n; float wtavg, tatavg;clrscr();printf("\nEnter the number of processes -- "); scanf("%d", &n); for(i=0;i<n;i++){printf("\nEnter Burst Time for Process %d -- ", i); scanf("%d", &bt[i]);}wt[0] = wtavg = 0; tat[0] = tatavg = bt[0]; for(i=1;i<n;i++){wt[i] = wt[i-1] +bt[i-1];tat[i] = tat[i-1] +bt[i]; wtavg = wtavg + wt[i]; tatavg = tatavg + tat[i];}printf("\t PROCESS \tBURST TIME \t WAITING TIME\t TURNAROUND TIME\n");for(i=0;i<n;i++){printf("\n\t P%d \t\t %d \t\t %d \t\t %d", i, bt[i], wt[i], tat[i]);}printf("\nAverage Waiting Time -- %f", wtavg/n);printf("\nAverage Turnaround Time -- %f", tatavg/n); getch();}
Modiflow y the beprogram given to include response time program;FCFS CPU SCHEDULING ALGORITHM #include<stdio.h>#include<conio.h>main(){int bt[20], wt[20], tat[20], i, n; float wtavg, tatavg;clrscr();printf("\nEnter the number of processes -- "); scanf("%d", &n);for(i=0;i<n;i++){printf("\nEnter Burst Time for Process %d -- ", i); scanf("%d", &bt[i]);}wt[0] = wtavg = 0; tat[0] = tatavg = bt[0];for(i=1;i<n;i++){wt[i] = wt[i-1] +bt[i-1];tat[i] = tat[i-1] +bt[i]; wtavg = wtavg + wt[i]; tatavg = tatavg + tat[i];}printf("\t PROCESS \tBURST TIME \t WAITING TIME\t TURNAROUND TIME\n");for(i=0;i<n;i++){printf("\n\t P%d \t\t %d \t\t %d \t\t %d", i, bt[i], wt[i], tat[i]);}printf("\nAverage Waiting Time -- %f", wtavg/n);printf("\nAverage Turnaround Time -- %f", tatavg/n); getch();}
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