Assume a 5-stage pipelined CPU (IF – ID – MU– EX – WR) requires following time for different sections: Pipeline stages ----Required time Fetch Unit ---15 ns Decode Unit ---10 ns Memory Unit---- 20 ns Execution Unit---- 8 ns Write back Unit ----15 ns The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. Assume the condition is evaluated TRUE.

Assume a 5-stage pipelined CPU (IF – ID – MU– EX – WR) requires following time for different sections: Pipeline stages ----Required time Fetch Unit ---15 ns Decode Unit ---10 ns Memory Unit---- 20 ns Execution Unit---- 8 ns Write back Unit ----15 ns The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. Assume the condition is evaluated TRUE.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 3PE: Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
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Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations, and 5 cycles for branches, and 4 cycles for memory operations. Assume that the relative frequencies of these operations are60%,20%, and20%respectively. Suppose that due to clock skew set up, pipelining the processor adds0.2 nsof overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline? Please type answer no write by hend.
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
A multiprocessor consists of 100 processors, each capable of a peak execution rate of 2Gflops. What is the performance of the system as measured in Gflops when 2% of the code is sequential and 98% is parallelizable?
A hypothetical processor has 9 stages of a pipeline as shown in the table below. The first row in the table below shows the pipeline stage number, second row gives the name of each stage, and third row gives the delay of each stage in Nano-seconds. The name of each stage describes the task performed by it. Each stage takes 1 cycle to execute. This processor stores all the register contents in a compressed fashion. After fetching the operands the operands are first decompressed, and before saving the results in register file, the results are first compressed. a)How many cycles are required to execute one instruction on this pipeline? b)How many cycles are required to execute 19 instructions on this pipeline? Assume that no stall cycles occur during the execution of all instructions. c) Assume that all necessary bypass/forwarding circuitry is implemented in this 9 stage pipeline. How many cycles will the pipeline stall during the execution of below given two instructions? Briefly explain…
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ANSWER THE QUSTIONS THAT IS WRITEN OR ON THE PICTURE PLEASE Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing. Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing. Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.