The of a machine specifies the instructions that the computercan perform and the format for each instruction.ISA (instruction set architecture)ISSAIA A digital computer has a memory unit with 32 bits per word. Theinstruction set consists of 110 different operations. All instructionshave an operation code part (opcode) and two address fields: one fora memory address and one for a register address. This particularsystem includes eight general-purpose, user-addressable registers.Registers may be loaded directly from memory, and memory may beupdated directly from the registers. Direct memory-to-memory datamovement operations are not supported. Each instruction stored inone word of memory. At least, how many bits are needed for theopcode?

QUESTION 1: The ---------- of a machine specifies the instruction that the computer can perform and…

Answered: The of a machine specifies the…

The of a machine specifies the instructions that the computer can perform and the format for each instruction. O ISA (instruction set architecture) O IS SA O IA

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 4PE

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.
Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
Under the von Neumann architecture, a program and its dataare both stored in memory. It is therefore possible for a program,thinking that a memory location holds a piece of data when itactually holds a program instruction, to accidentally (or onpurpose) modify itself. What implications does this present to youas a programmer?
You have been contrated to design a memory system for a computer. Assuming the processor has 32 address lines, determine the number of 32 MB memories that can be placed (without overlapping) in the memory space of a processor.
Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16-bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it connected to an “8-bit memory”? What architectural features will allow this microprocessor to access a separate I/O spece? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports can the microprocessor support? Are the values in d and e the same?
Consider a hypothetical microprocessor generating a 16-bit address (e.g., assume the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”? What architectural features will allow this microprocessor to access a separate “I/O space”? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.
Under the von Neumann architecture, a program and its data are both stored in memory. Itis therefore possible for a program, thinking a memory location holds a piece of data when it actually holds a program instruction, to accidentally (or on purpose) modify itself. Whatimplications does this present to you as a programmer?
Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “50” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
2. This question is about Digital Logic and Address DecodingA computer is being designed using a microprocessor with a 16-bit address bus (A0—A15, where A0 is the least significant bit). The 64K address space is to be split betweenand allocated to RAM, ROM and I/O hardware as follows:Address Range (hex) Contains Select Signal0x0000 — 0x1FFF Main RAM RAMCS0x8000 — 0x9FFF Video RAM VRAMCS0xB000 — 0xBFFF I/O hardware IOCS0xC000 — 0xCFFF BASIC ROM BROMCS0xF000 — 0xFFFF OS ROM OSROMCSThe rest of the address space is unused.Note: As with many computer systems, it its only necessary to decode addresses to sufficiently identify each of the sections above uniquely. It is acceptable for some parts to be decodeable by more than one address provided these extra addresses do not overlap any of the other specified address ranges. Using a combination of AND, OR and NOT gates and the signals (A12 — A15) that contain the top four bits of the address in binary form: a. Derive the equation for a logic…
I want all steps for Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “7” computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
Consider a word-addressable computer with 32 bits per word. The instruction set consists of 30 different All instructions have an operation code field, a mode field to specify one of 7 possible addressing modes, a register address field to specify one of 60 available registers, and a memory address field. Each instruction is stored in one word of memory. What is the maximum allowable size for memory? Use KB, MB, or GB as a unit.