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- A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-backcache (i.e., each block needs a dirty bit). The cache implements a true LRU replacement policy usingthe minimum number of replacement policy bits necessary to implement it, which means it requires 3bits per set. The tag store requires a total of 264 bits of storage. What is the block size of the cache?(Hint: 264 = 2^8 + 2^3 and please also do not forget that aside from the tag itself, each block needs 1valid bit, 1 dirty bit).Suppose the Vole communicates with a printer using the technique of memory-mapped I/O. Suppose also thataddress 0xFF is used to send characters to the printer, and address 0xFE is used to receive information about theprinter’s status. In particular, suppose the least significant bit at the address 0xFE indicates whether the printeris ready to receive another character (with a 0 indicating “not ready” and a 1 indicating “ready”). Starting ataddress 0x00, write a machine language routine that waits until the printer is ready for another character and thensends the character represented by the bit pattern in register 0x5 to the printer.What are the contents of the 25 memory bytes starting at address A, in hex, on a machine that uses Little Endian? (Hint: “a”=061h) Consider the following .data segment: A dw 0AAFFh B db 051h, 0CCh, 0EEh C times 3 dw -23 D dd -177 E db "e", -5, "c", 0 F times 2 dw -17 G dw 0EEh
- Question: Show the execution of each line of the given MIPS Code for $s0 = 0xA starting from“Main” till the code reaches “End”.Main: ble $s0, $0, Endsub $a0, $s0, $0Jal FuncJ EndFunc: add $v0, $0, $0Loop: addi $v0, $v0, 1srl $a0, $a0, 1bgt $a0, $0, LoopRet: jr $raEnd:What is the tmiss time for the following set up: Block size = 32, time for address = 20 cycles, time for data transfer = 5 cc. tmiss will be found in the following ways. a) no optimization b) K= 4, M=2 c) K=4, M=4In 32-bit mode, aside from the stack pointer(ESP), what other register points to variables on the stack? Name at least four CPU status flags. Which flag is set when the result of an unsigned arithmetic operation is too large to fit into the destination? Which flag is set when the result of a signed arithmetic operation is either too large or too small to fit into the destination? (True/False): When a register operand size is 32 bits and the REX prefix is used, the R8D register is available for programs to use. Which flag is set when an arithmetic or logical operation generates a negative result? Which part of the CPU performs floating-point arithmetic? On a 32-bit processor, how many bits are contained in each floating-point data register? (True/False):The x86-64 instruction set is backward-compatible with the x86 instruction set. (True/False): In current 64-bit chip implementations, all 64 bits are used for addressing. (True/False):The Itanium…
- Some computers have an instruction that atomically exchanges the values of two memorylocations. It is defined as follows:Exchange(int var1, int var2):⟨ int temp; temp = var1; var1 = var2; var2 = temp; ⟩Above, temp is an internal machine register.Using Exchange, dev elop a solution to the critical section problem. In particular, giv ecode forCSenter and CSexit protocols that use the shared lock variable declared below. Y our solutiondoes not have to be fair.shared variable: int lock = 0;CSenter:CSexitGiventhe following assignment of some program’s virtual pages to physical pages in a system with 4 KiB byte pages, what physical memory address corresponds to virtual address 20000? (All values are given in decimal.)write the following questions a) Write an 8051 C program to send Hex values for ASCII characters of 0,1,2,3,4,5AB,C and D to port P1 b) Interface a 4X4 keyboard with 8086 using 8255, and write an ALP for detecting a key closure and return the key code in AL. The debouncing period for a key in 20 ms
- Solve the 8085 Write a program to load twenty memory locations starting from 8005H, where each location's content should increases by 2 over the previous one, however, the first location should contain 04H, assuming that the programs start at memory location 9009H?Suppose, you need to service 36 interrupts. At least how many slave-8259chips do you need to fulfil this requirement? Again, let, you need one more interrupt to servicealongside the above 36. Would you need more slave-8259? Explain shortly.Is there anything that ought to take place if a processor sends a cache-unfulfilled request at the same time as a block is being sent back to main memory from the write buffer?