what are output voltages caused by logic 1 in each bit positionin 8 bit ladder if  the input level for 0 is 0v and for 1 is 10v

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
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what are output voltages caused by logic 1 in each bit positionin 8 bit ladder if  the input level for 0 is 0v and for 1 is 10v?

 

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