Which of the following attributes is associated with RISC architecture? Group of answer choices a) AMD64/Intel64/X86-64 is an example of a RISC ISA b) Each instruction does as much computation as possible so that instruction fetch and decode overhead is relatively small c) Instructions tend to use very simple encoding, often fixed length d) Instructions like add can have one operand accesed directly from memory e) Arguments to functions are always passed on the stack

Which of the following attributes is associated with RISC architecture? Group of answer choices a) AMD64/Intel64/X86-64 is an example of a RISC ISA b) Each instruction does as much computation as possible so that instruction fetch and decode overhead is relatively small c) Instructions tend to use very simple encoding, often fixed length d) Instructions like add can have one operand accesed directly from memory e) Arguments to functions are always passed on the stack

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 4PE

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
The register content for an Intel 8086 microprocessor is as follows:CS = 1000H, DS = 2000H, SS = 5000H, SI = 2000H, DI = 4000HBX = 6783H, BP = 7000H, AX = 29FFH, CX = 8793H, DX = A297HCalculate the physical address of the memory where the operand is stored and the contents of the memory locations in each of the addresses shown below: a) MOV [SI], ALb) MOV [DI+6H], BXc) MOV [SI+BX–11], AXd) MOV [DI][BX]+28H, CXe) MOV [BP][SI]+17, DX
Consider a 16-bit processor in which the following appears in the main memory, starting at location 200.a. The first part of the first word (content at 200) indicates that this instruction loads a value into an accumulator; the value of 300 in location 201 may be part of the address calculator. The mode field specifies an addressing mode and, if appropriate, indicates a source register. a. Assume that when used, the source register R1, which has a value of 500. b. There is also a base register that contains the value 100, Assume that location 249 contains the value 399, location 250 contains the value 400, and so on. Determine the effective address and the operand to be loaded for the following address modes:
Which of the following is False regarding RISC and CISC architectures? a) CISC has variable length instruction formats while RISC has fixed length instructions . b) CISC has a larger number of instructions than RISC. c) CISC has more addressing modes than RISC. d) In RISC, memory access is limited to load and store instructions, while in CISC, other instructions can support memory access e) CISC has a larger number of general purpose registers than RISC.
We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.
The NOR instruction is not part of the RISC-V instruction set because the samefunctionality can be implemented using existing instructions. Write a short assembly codesnippet that has the following functionality: s3 = s4 NOR s5. Use as few instructions aspossible. Write RISC-V assembly code for placing the following immediate constants inregister s7. Use a minimum number of instructions.a) 59b) -199c) 0xDDCBE289d) 0x11236BDF
1) For a Pentium II descriptor that contains a base address of 0004B100H, a limit of 00FFFH, and G = 1, what starting and ending locations are addressed by this descriptor? 2) Code a descriptor that describes a memory segment that begins at location 0005CF00h and ends at location 00060EFFh. The memory segment is a data segment that grows upward in the memory system and can be written. The segment has a user level privilege (lowest) and has not been accessed. The descriptor is for an 80386 microprocessor.
Consider the following store instruction: SW R1, 0x000F(R0). Assume that the registers R0 and R1 are initialized with 0x00000001 and 0x53A78BC Frespectively. A section of the MIPS byte addressable data memory is shown. Give the memory word of the following memory locations after the SW operation: (a). 0x00000015. (b). 0x00000014. (c). 0x00000013. (d) 0x00000012.(e). 0x00000011. (f). 0x00000010.
Design a simple microprocessor called Ege-ARM which is a simple 16-bit single-cycle processor that implements a custom instruction set. The processor should consist of the following four main components:- A register file- An Arithmetic and Logic Unit (ALU)- A read-only instruction memory (IMEM)- A read/write data memory (DMEM) This processor has 8 registers (R0-R7) and the program code is stored as 22-bit instructions in the IMEM. The processor implements three types of instructions, an instruction format example for 22-bit instructions is shown at Table 1. Some instruction examples are shown at Table 2.
The Kiwi™ memory architecture design team has a dilemma. The team is considering several different memory configuration variations for an upcoming machine design. Consider the following designs (All memory accesses are in terms of bytes, and all are using paging techniques): Characteristic Design 1 Design 2 Design 3 Physical Memory Address Width 8 bit 16 bit 32 bit Logical Address Width 12 bit 20 bit 24 bit Page/Frame size in bytes 16 bytes 32 bytes 64 bytes Page Table Type Single Single Double a) For each design, list the maximum number of pages each process can access in logical address space. b) For each design, list the maximum number of frames in physical memory.
2. This question is about Digital Logic and Address DecodingA computer is being designed using a microprocessor with a 16-bit address bus (A0—A15, where A0 is the least significant bit). The 64K address space is to be split betweenand allocated to RAM, ROM and I/O hardware as follows:Address Range (hex) Contains Select Signal0x0000 — 0x1FFF Main RAM RAMCS0x8000 — 0x9FFF Video RAM VRAMCS0xB000 — 0xBFFF I/O hardware IOCS0xC000 — 0xCFFF BASIC ROM BROMCS0xF000 — 0xFFFF OS ROM OSROMCSThe rest of the address space is unused.Note: As with many computer systems, it its only necessary to decode addresses to sufficiently identify each of the sections above uniquely. It is acceptable for some parts to be decodeable by more than one address provided these extra addresses do not overlap any of the other specified address ranges. Using a combination of AND, OR and NOT gates and the signals (A12 — A15) that contain the top four bits of the address in binary form: a. Derive the equation for a logic…