Write the following assembly language codes: a) Write a single instruction to add the carry flag to register AH. b) Write the code to find the number of 1s in the register AL. c) Write the code to place 1 in register AL if the value in BL is odd. d) Declare two byte values and find the sum of the values and place the value in a byte location called sum, multiply the values and place in a word location called product and divide the values and save the quotient and remainder in byte locations called quotient and remainder.
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- 38. Implement the following expression in assembly language, using 32-bit integers (you may modify any registers you wish): eax = -dword1 + (edx - ecx) + 1 You can use this data definition for testing your code: dword1 DWORD 10h 39. se the following data declarations to write an assembly language loop that copies the string from source to target. Use indexed addressing with EDI, and use the LOOP instruction source BYTE "String to be copied",0 target BYTE SIZEOF source DUP(0),0For the MIPS assembly instructions below, what is the corresponding C statement?Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and$s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t1, $s1, 2add $t1, $t1, $s6lw $t1, 0($t1)sub $t0, $s3, $s4sll $t0, $t0, 2add $t0, $t0, $s7lw $t0, 0($t0)add $t1, $t1, $t0sll $t0, $s0, 2add $t0, $t0, $s7sw $t1, 0($t0)Question 10 The JZ instruction changes the flags Group of answer choices True False Question 11 The hexadecimal number 31 36 can be interpreted as representing a decimal number _________ or a pair of ASCII codes _________. Group of answer choices 12598 16 12598 61 12589 16 none of them : Question 12 Assume that EBX and ECX have the following values EBX: FF FF FF 75 ECX: 00 00 01 A2 After the execution of the instruction SUB EBX, ECX The Value in ECX is _________ Group of answer choices 000001A2 FFFFFDD3 00000000 none of them
- Assume a CPU with a fixed 32-bit instruction length has the following instruction format:opcode mode [operand1] [operand2] [operand3]The mode encodes the number of operands and each operand’s mode. For instance, one mode indicates three registers, another indicates two registers and an immediate datum, another indicates a main memory reference, etc. Assume there are 94 instructions and 22 modes. Answer the following.a. One mode indicates three registers. How many registers can be referenced in this mode?b. One mode indicates two registers and an immediate datum in two’s complement. Assuming there are 32 registers, what is the largest immediate datum that can be referenced?c. One mode has a destination register and a source memory address (an unsignednumber). Assuming 16 registers, what is the largest memory reference available?d. One mode has two memory addresses, both using base displacement. In both, the basesare stored in index registers and the displacements are specified in the…Write an assembly language instruction that has five WORD size variables in its data section as follows: num1 WORD 5 num2 WORD 7 num3 WORD 8 num4 WORD 9 result WORD ? Write an assembly language program that adds num1 + num2 + num3 + num4 and places the result in result. Note that do not add two memory locations in one instruction.Convert given code to LEGv8 code:int f, g, y //global 64-bit variablesint sum (int a, int b) { // at memory address X0+1000.return (a +b)} int main (void) // at memory address X0 + 800{f=2;g=3;y= sum (f, g);return y;}Convert this code, making valid assumptions about registers and register use. Notethat brackets and global variable declarations are not affecting the addresses of the instructionsin memory.
- 2. For the following C statement, what is the corresponding MIPS assembly code? Assume that the C variables a, b, and c, have already been placed in registers $s0, $s1, $s2, respectively. Use a minimal number of MIPS assembly instructions. a = b + (c − 5); 3. For the following C statement, write the corresponding MIPS assembly code. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[i-j] = A[8]; 4.Translate the following C code to MIPS. Assume that the variables, f,g. h, i, and j are assigned to registers $s0, $s1, $s2, $s3, $s4, and $s4, respectively. Assume that the base address of A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 8-byte words: B[8] = A[i] + A[j]; 5.For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the…For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays (A and B) are in registers $s6 and $s7, respectively. Also, assume that A and B are arrays of words. B[f-j] = B[i] + A[g]Question Write an assembly code to implement the y = (x1+x2) * (x3+x4) expression on 2-address machine, and then display the value of y on the screen. Assume that the values of the variables are known. Hence, do not worry about their values in your code. The assembly instructions that are available in this machine are the following: Load b, a Load the value of a to b Add b, a Add the value of a to the value of b and place the result in b Subt b, a Subtract the value of a from the value of b and place the result in b Mult b, a Multiply the values found in a and b and place the result in b Store b, a Store the value of a in b. Output a Display the value of a on the screen Halt Stop the program Note that a or b could be either a register or a variable. Moreover, you can use the temporary registers R1 & R2 in your instructions to prevent changing the values of the variables (x1,x2,x3,x4) in the expression. In…
- 3. For the following C statement, write the corresponding MIPS assembly code. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[i-j] = A[8]; 4.Translate the following C code to MIPS. Assume that the variables, f,g. h, i, and j are assigned to registers $s0, $s1, $s2, $s3, $s4, and $s4, respectively. Assume that the base address of A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 8-byte words: B[8] = A[i] + A[j]; 5.For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. You must add line comments to ALL uncommented 4 lines. sll $t0, $s0, 2 #…For the next two questions, consider the following portion of assembly code, which places two quad-word (64-bit) values in memory, and names the locations a and b respectively. .align 8 a: .quad 0xaaaa b: .quad 0x0000 (e) Provide a sequence of instructions that will place the 64-bit value at memory location a into register %rdx (f) Provide a sequence of instructions that will place the 64-bit value 0xbbbb into memory at location b.6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…