15 Part 1 of 2 L1 Inputs O O-S1 0-S2 2 O-S3 O O-S4 o-S5 1 o S6 3 5- 6 7 8 S1 HE S2 HF S3 HE S4 = HE S155 36 S6 36 Ladder logic program · ΤΟΝ TIMER ON DELAY Timer Time base Preset Accumulated (MCR) PL1 () PL2 PL2 (u) (MCR) (MCR) T4:1 1:0 10 0 MCR (EN) (ON) PL1 PL2 Outputs L2 OF With switches S2 and S3 still on and switch S1 turned on now, both the outputs PL1 and PL2 come o
15 Part 1 of 2 L1 Inputs O O-S1 0-S2 2 O-S3 O O-S4 o-S5 1 o S6 3 5- 6 7 8 S1 HE S2 HF S3 HE S4 = HE S155 36 S6 36 Ladder logic program · ΤΟΝ TIMER ON DELAY Timer Time base Preset Accumulated (MCR) PL1 () PL2 PL2 (u) (MCR) (MCR) T4:1 1:0 10 0 MCR (EN) (ON) PL1 PL2 Outputs L2 OF With switches S2 and S3 still on and switch S1 turned on now, both the outputs PL1 and PL2 come o
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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