3. CPU x86/8088 executes the instruction ADD AX, CX; 2byte instruction, machine code is (03-C1). Before executing this instruction, CS=4200, IP = A000, AX = 7000, CX = 3000, (all data in hexadecimal). • Describe this command, Draw a block diagram with signal and bus timing diagram to describe its operation for 8bit data bus system, • Contents of CPU's registers before and after executing this instruction • What flag(s) will be affected after executing? %D

3. CPU x86/8088 executes the instruction ADD AX, CX; 2byte instruction, machine code is (03-C1). Before executing this instruction, CS=4200, IP = A000, AX = 7000, CX = 3000, (all data in hexadecimal). • Describe this command, Draw a block diagram with signal and bus timing diagram to describe its operation for 8bit data bus system, • Contents of CPU's registers before and after executing this instruction • What flag(s) will be affected after executing? %D

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
1, Explain how we can find the address location of INT 0AH in Interrupt vector table. 2. What will be the content of AX register after execution of the instruction IMULCL, if CL = +1510 and AL = -13210.. 3. Suppose that DS = 1300H, SS = 1280H, BP = 15A0H and SI = 01D0H.Determine the address accessed by each of the following instructions andmention their type of addressing mode.i) MOV AX, [200H]ii) MOV AL, [BP-SI+200H]iii) ADD AL, [SI + 0100H]
Assuming stall-on-branch and no delay slots, what is the new clock cycle time and execution time of this instruction sequence if beq address computation is moved to the MEM stage? What is the speedup from this change? Assume that the latency of the EX stage is reduced by 20 ps and the latency of the MEM stage is unchanged when branch outcome resolution is moved from EX to MEM.
The following problems are related to Complete Organization and Architecture related problems. 1. a.Following packed SIMD data type of X86 architecture interpret packed single precision and packed double precision floating point numbers with and example. Suppose that two registers contain two hexadecimal values A023CC92 and 4588DE78. What is the result of adding those using MMX instructions as packed byte, assume saturation arithmetic is not used? b. Explain the difference between a simple CAV system and a multiple zone recording system.
Assume the usage of ARM assembly language instruction: STR R0,[R1],#0x8. Assume that Register R0 contains 0xA0, Register R1 contains 0x7008. Identify (i) contents of memory location 0x00A8 and (ii) R1 after executing the given instruction (i) 0xA0, (ii) 0x7008 (i) 0xA0, (ii) 0x7011 (i) 0xA2, (ii) 0x7008 (i) 0xA2, (ii) 0x7010
Consider the following store instruction: SW R1, 0x000F(R0). Assume that the registers R0 and R1 are initialized with 0x00000001 and 0x53A78BC Frespectively. A section of the MIPS byte addressable data memory is shown. Give the memory word of the following memory locations after the SW operation: (a). 0x00000015. (b). 0x00000014. (c). 0x00000013. (d) 0x00000012.(e). 0x00000011. (f). 0x00000010.
Considering the following MIPS assembly code snippet. mydata: .word 0x01020304, 0x05060708, 0x090A0B0C0, 0x0D0E0F10, 0xE0001211, 0xA031023A … li $t1, 1 sll $t1, $t1, 2 lb $s0, mydata($t1) What is the value of register $s0 after the instruction lb was executed? _________ Please provide an answer and an explanation.
suppose that ds=b9dc, ss=f7ca, es=ab32, ax=dc5, di=8e9, bx=d98, bp=2ce, si=97d, var1=12a and var2=d32. determine the content of the destination after executing the instruction mov cx, [si+dfe], assuming real mode.
In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code: sw r16,12(r6)lw r16,8(r6)beq r5,r4,Label # Assume r5!=r4add r5,r1,r4slt r5,r15,r4 Assume that individual pipeline stages have the following latencies: IF ID EX MEM WB200ps 120ps 150ps 190ps 100ps 1.1, For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the 5-stage pipeline that only…
cs 218 assembly language Given the code fragment: lst dd 2, 3, 5, 7, 9 mov rsi, 4 mov eax, 1 mov rcx, 2 lp: add eax, dword [lst+rsi] add rsi, 4 loop lp mov ebx, dword [lst] What would be in the eax and ebx registers after execution (in hex)? eax ebx Must answer in hex (must precede number with 0x) .
Th is exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath:add r5,r2,r1lw r3,4(r5)lw r2,0(r2)or r3,r5,r3sw r3,0(r5)> If there is no forwarding or hazard detection, insert nops to ensure correct execution.> Repeat above step, but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary values in your modifi ed code.> If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes?
By using an equation off = ( a - b ) / [ ( d x e ) + c ];(a) illustrate the step to realize this equation by using the stack concept. (b) construct its’ CISC zero address format. (c) construct its CISC one address format. (d) construct the CISC two address format by using only 3 register. (e) In your opinion, do we need to have at least as possible instruction line? Do it will reflectthe performance of computer execution time?