By using an equation of f = ( a - b ) / [ ( d x e ) + c ]; (a) illustrate the step to realize this equation by using the stack concept. (b) construct its’ CISC zero address format. (c) construct its CISC one address format. (d) construct the CISC two address format by using only 3 register. (e) In your opinion, do we need to have at least as possible instruction line? Do it will reflect the performance of computer execution time?
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By using an equation of
f = ( a - b ) / [ ( d x e ) + c ];
(a) illustrate the step to realize this equation by using the stack concept.
(b) construct its’ CISC zero address format.
(c) construct its CISC one address format.
(d) construct the CISC two address format by using only 3 register.
(e) In your opinion, do we need to have at least as possible instruction line? Do it will reflect
the performance of computer execution time?
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- A program stack is to use 800 h bytes and SS= 0300 h, A = 1234 h and B = 6AB3 h. Shows the contents of the stack, stack pointer, and physical address using appropriate diagram after the instruction PUSH BXConsider the following expression: R = U*(V + W/X – Y*Z). List a sequence of instructions to evaluate this expression on a stack-based architecture with zero-address arithmetic instructions (ADD, SUB, MUL, DIV), and PUSH and POP instructions.Develop a hypothetical architecture with illustrative instruction and data formats, instruction sets, etc., explain the instruction and machine cycles step-by-step by developing a short program (at least, with two arithmetic operations, three logic operations, three memory or two L/C) operations) and by indicating the corresponding register operations. All architectural, etc., selections must to be justified sufficiently. CAN YOU EXPLAIN WITH THE EXAMPLE USING NUMBERS IN THE STACKS WITH EACH STEP INSTEAD OF PROGRAM.
- 5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. (a) Suppose all instructions and operands are one byte long, by what factor do the maximum data transfer rates differ?Considering the following contents of Stack Segment (SS) Register and Stack Pointer (SP) Register: SS = A5B0H, SP = 4DF0H (a) Calculate the values of Top of Stack (ToS) and Bottom of Stack (BoS)? (b) Consider the following operations on the stack: PUSH AX PUSH [CX] PUSH 10 POP [BX] POP AX What is the value of ToS after all these operations? Also, provide the value of ToS after each instruction.Explain the Register stack organization of 32 locations of the stack (0 to 31 ). take the initial value of the stack pointer is SP = 09 in Hex. Explain the following push and pop instructions through the Register stack organization diagram.(1) PUSH R2 WHERE R2 = XX in Hex(2) POP R1 WHERE R1 = (XX + 5 ) in Hex where XX is your class roll no , for example roll no 64 is having the data in R2 = 64 Hex and R1=( 64+5 = 69 Hex)
- Computer Architecture (Already submit this question, but I think I got wrong solution) Consider a computer that has a number of registers such that the three registers R0 =1500, R1 = 4500, and R2 = 1000 Show the effective address of memory and the registers’ contents in each of the following instructions 1. ADD (R1), R2 2. MOVE 500(R0), R2 3. ADD (40), R1 4. SUBTRACT (5000), R2 5. ADD #30, R2Fill in blank Suppose that segmentation method is used for memory management. Process A has these three values in its base registers: 32KB for code segment, 34KB for heap segment, and 28KB for stack segment. In the virtual memory of process A, the code segment takes the space from 0KB to 2KB, where its base register provides the relocation of 0KB. The heap segment takes the space from 4KB to 7KB, where its base register provides the relocation of 4KB. To fetch an instruction at virtual address 205, the kernel will use physical address ---------- (in decimal). To load a value to a register from the heap location with virtual address 4300, the kernel will use physical address ----------The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=800 T1=200 T2=200 T3=300
- The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction.The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Immediate Mode Direct Mode Register Relative Mode Index ModeNote: Choose your own values for variables k – w, T1, T2. Choose any one of the given value for T3 (200 or 300).What is the concept of VLIW (Very Long Instruction Word) architecture, and how does it exploit instruction-level parallelism?17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…