4.J DRg ue NMUS TieluEeer aSISO TOT 1.5 M2 R, 75 k2 Rp 1.5 M2 2 R2 75 k2 Rp V pD 10 V 10 V 10 V VDD R, 1 ΜΩ 39 k2 Rs VIN =1 V K.- 25 μΑ/V 39 k2 Rs 1 ΜΩ R1 (a) (b) Figure 4.27 (a) Four-resistor bias network for a MOSFET; (b) equivalent circuit with replicated sources.

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Redraw the circuit  with a four-terminal
NMOS transistor with its body connected to −3 V

4.J DRg ue NMUS TieluEeer aSISO
TOT
1.5 M2 R,
75 k2
Rp
1.5 M2 2 R2
75 k2
Rp
V pD
10 V
10 V
10 V
VDD
R,
1 ΜΩ
39 k2
Rs
VIN =1 V
K.- 25 μΑ/V
39 k2
Rs
1 ΜΩ
R1
(a)
(b)
Figure 4.27 (a) Four-resistor bias network for a MOSFET; (b) equivalent circuit with replicated sources.
Transcribed Image Text:4.J DRg ue NMUS TieluEeer aSISO TOT 1.5 M2 R, 75 k2 Rp 1.5 M2 2 R2 75 k2 Rp V pD 10 V 10 V 10 V VDD R, 1 ΜΩ 39 k2 Rs VIN =1 V K.- 25 μΑ/V 39 k2 Rs 1 ΜΩ R1 (a) (b) Figure 4.27 (a) Four-resistor bias network for a MOSFET; (b) equivalent circuit with replicated sources.
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