5 (a). Design a 2-bit up-counter using JK FFs with negative edge triggered clock and states as [Q1 Q0]. You must explain the working towards your answer such as state diagram, state table, excitation table, simplified input equations, state equations and the designed circuit. 5 (b). Write the state equations for the sequential circuit shown in Fig. 5.1.

5 (a). Design a 2-bit up-counter using JK FFs with negative edge triggered clock and states as [Q1 Q0]. You must explain the working towards your answer such as state diagram, state table, excitation table, simplified input equations, state equations and the designed circuit. 5 (b). Write the state equations for the sequential circuit shown in Fig. 5.1.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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3(a): Consider the following circuit, which uses two D flip-flops with falling edge triggers along with -bit full adder. The flip-flops are controlled by a single clock, C. Suppose C, Q0 and Q1 all initially have the value 0. First, fill in the blanks in the "i " = 0 (initial state)" row to show the values of D0 and D1 at this initial time (assume the results of the adder have had time to stabilize) . Next, show the values of Q0 , Q1, D0 , and D1 once they have stabilized after the ith falling edge of the clock, where i ranges from 1 to 4. Note that both the A and Carry In inputs of the adder are (Q not ) Q'0 not Q0 None of these first four rows should be the exactly the same.
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