1. Implement the circuit F(A, B, C, D) = [I(O, 2, 5, 7, 10, 11, 13, 14, 15) using multiplexers and external logic gates. (30 points) a. Show the truth table in order of mux input groupings for each case below. (10 points) b. Show your work in creating the minimized Boolean POS expressions for each multiplexer. You may use any combination of K-maps and'or Boolean algebra. (10 points) c. Write a Verilog module for the case I circuit. Use bitwise operations for the external logic gates and named instantiation of the mux module. Assume the mux module already exists and has the following name and port list. (10 points) module mux4to1(input wire [1:0] s, input wire [3:0] dataln, output wire m); Case 1: A, B are the select bits. Case 2: C is the select bit.

Database System Concepts
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ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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1. Implement the circuit F(A, B, C, D)=[[0, 2, 5, 7, 10, 11,
13, 14, 15) using multiplexers and external logic gates. (30
points)
a. Show the truth table in order of mux input groupings
for each case below. (10 points)
b. Show your work in creating the minimized Boolean
POS expressions for each multiplexer. You may use
any combination of K-maps and/or Boolean algebra.
(10 points)
c. Write a Verilog module for the case I circuit. Use
bitwise operations for the external logic gates and
named instantiation of the mux module. Assume the
mux module already exists and has the following
name and port list. (10 points)
module mux4to1(input wire [1:0] s, input wire [3:0]
dataln, output wire m);
Case 1: A, B are the select bits.
Case 2: C is the select bit.
Transcribed Image Text:1. Implement the circuit F(A, B, C, D)=[[0, 2, 5, 7, 10, 11, 13, 14, 15) using multiplexers and external logic gates. (30 points) a. Show the truth table in order of mux input groupings for each case below. (10 points) b. Show your work in creating the minimized Boolean POS expressions for each multiplexer. You may use any combination of K-maps and/or Boolean algebra. (10 points) c. Write a Verilog module for the case I circuit. Use bitwise operations for the external logic gates and named instantiation of the mux module. Assume the mux module already exists and has the following name and port list. (10 points) module mux4to1(input wire [1:0] s, input wire [3:0] dataln, output wire m); Case 1: A, B are the select bits. Case 2: C is the select bit.
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