A diagram for a traffic light control
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- CREATE A FSM STATE DIAGRAM USING THE FOLLOWING INFORMATION:The system has four states, which represent the current level of the elevator (inorder from highest level to lowest level): Entrance Floor (ground level), EmployeeParking (first underground level), Underground Parking 2 (one level below em-ployee parking), Underground Parking 3 (two levels below employee parking)•The system has two 1-bit inputs: Up (label: u), Down (label: d)•The system has one 2-bit output: Level (label: L or L1 and L0 for each individualbit, where index 1 indicates the MSB and index 0 the LSB) •If the Up button is pressed, the elevator goes to the level above. If the elevator isalready in the highest level, pressing the Up button will have no effect and will stayin the current level. In case the level above is the employee parking, the elevatorwill skip this level and go directly to the level above it.•If the Down button is pressed, the elevator goes to the level below. If the elevatoris already in…Given five inputs (a, b, c, d, e) connected to 8051’s port P1 and P2 with : P1.0 = a, P2.0 = b, P1.3 = c, P2.7 = d et P1.6 = e. Outputs S0 and S1 are connected to P3.0 and P3.1 respectively as shown in the figure below. We propose to realize the following logic S0 = a.b + c.d + e.(a.b + a.b) S1 = c.b + d + e.a.bFor a rising-edge T-FF, Complete the following timing diagram (assume that Q = 0 initially). Which answer represent the correct output description? 1. Q changes its value at time 2 from 0 to 1, and time 4, from 1 to 0. 2. Q changes its value at time 1 from 0 to 1, and time 2, from 1 to 0. 3. Q changes its value at time 1 from 1 to 0, and time 3, from 0 to 1. 4. None 5. Q changes its value at time 2 from 1 to 0, and time 3, from 0 to 1.
- Draw the control unit and datapath for the following algorithm that returns an integer value. The function takes two points (x1, y1) and (x2, y2) and computes the equation for a line. It then evaluates and returns ynew for the parameter xp using that line. Use a 16-bit data bus. Show your work; label and clearly mark your diagram. Do not implement this in VHDL. int PredY(int x1, int y1, int x2, int y2, int xp) { int m, b, ynew; if (x1 – x2) <> 0 { m = (y1 - y2) / (x1 - x2); b = y1 - m * x1; ynew = m * xp + b; return(ynew); } else { return(65535); // that's a 16-bit FFFF } }What's the purpose of this circuit diagram? At? Please identify the sandal kind. Why? ndmo ndmo ndmo ndmo ndmo ndmo ndmo is the following state. having a restConsider a special purpose decoder that is called BCD to seven-segment decoder. The decoder takes a 4-bit Binary Coded Decimal (BCD) number X3 X2 X4 X0 (0-9) and produces 7 outputs a, b, c, d, e, f, and g The specification of this circuit is as follows: ⚫ The 7 outputs of the decoder are connected to LED segments as shown in the figure below. The LEDs are active low, ie, the LED emits light when it is connected to logic 0. • The decoder output is determined in a way so that the LED segments display the decimal representation of the input. For example, if the input X3 X2 X1 X0 is 0001 respectively (which is equivalent to decimal 1), the outputs a, b, c, d, e, f, and gare 1001111 showing the letter 1 on the display (remember the LEDs are active low). Decoder W- 4x7 e U Answer the following questions: a. Fill in the truth table of that decoder. Choose a good value for the output when the input is greater than decimal 9. b. Derive the simplified Boolean expressions for the outputs a, b, c,…
- The fundamental distinctions between synchronous and isochronous connections will be explicated, and an instance of each will be presented.Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.Suppose you have an LFSR with state bits (also known as the seed) (s5,s4,s3,s2,s1,s0)=(1,1,1,0,1,1)(s5,s4,s3,s2,s1,s0)=(1,1,1,0,1,1) and tap bits (also known as feedback coefficients) (p5,p4,p3,p2,p1,p0)=(0,1,1,1,0,1)(p5,p4,p3,p2,p1,p0)=(0,1,1,1,0,1).What are the first 12 bits output by this LFSR?Please enter your answer in the form of unspaced binary digits (e.g. 010101010101). These come in order s0s1s2…s11s0s1s2…s11.
- Draw a state diagram of a High Level State Machine that describes the operation of a pulse generator. The generator should produce a pulse 10 clock cycles long, and pulse when an input goes high. Draw the state diagram of a High Level State Machine that describes the operation of a light sequencer for a traffic light. Green should be on for 100 clock pulses, yellow for 20 clock pulses, and red for 70 clock pulses, for this particular street direction. Assume a slow clock (0.25 seconds to 1 second per pulse). What would the opposing street traffic light requirements need to be? Design a High Level State Machine for a paid parking system, such as the one found at Minneapolis-St. Paul Airport. The system will take your credit card when you drive in, record the number and insure it is valid, and then when you depart it uses the same credit card and time stamp to determine how much to charge you.Design a circuit that has two inputs X, and S, where X represents an 8-bit BCD number, S is a sign bit. The circuit has one output Y, which is the Binary representation of the signed-magnitude BCD number. A negative output is represented in the Binary 2’s- complement form. You need to think of two design alternatives. Submission guidelines: 1. You should write a report that at least contains the following sections: 1. Problem definition. 2. Design alternatives : 2.1. Alternative 1 block diagram 2.2. Alternative 2 block diagram 3. Design selection criteria 4. Detailed circuit design of the selected alternative. 5. Verilog modules, and simulation results for all modules, and for the whole circuit of the selected alternative .157. The term that refers to the phase continues through the boundary of two signal elements is a. non coherent BFSK b. coherent BFSK c. Binary ASK d. Multilevel ASK