A Large Memory with the following buses: Address bus 32 bit. Data bus 32 bit. If we want to build this large memory using smaller memory chips of size 1024 X 8. A) How many 1024 X 8 ROM chips are needed? B) Each chip will need ____ address lines to address its internal memory cells C) What is the size of the decoder needed to be used

A Large Memory with the following buses: Address bus 32 bit. Data bus 32 bit. If we want to build this large memory using smaller memory chips of size 1024 X 8. A) How many 1024 X 8 ROM chips are needed? B) Each chip will need ____ address lines to address its internal memory cells C) What is the size of the decoder needed to be used

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 4PE

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
64-bit CPUs with 64-bit address buses can access 264 bytes of memory at a time. Do you think the need for virtual memory would go away if enough physical memory could be added to these systems in a cost-effective way? Say what you think about it.
Q2 . A computer employs RAM chips of 512 x 8 and ROM chips of 256 x 8. The computer system needs 1K bytes of RAM, 2K bytes of ROM, and eight interface units, each with 2 registers. A memory-mapped 1/0 configuration is used. The two highest-order bits of the 16 bit address bus are assigned 10 for RAM, 11 for ROM, and 00 for interface registers.a. How many RAM and ROM chips are needed?b. Draw a memory-address map for the system.c. Give the address range in hexadecimal for RAM, ROM, and interface.
We have a computer with a Direct Mapped Memory Cache. The main memory is 16GB and the cache is 64KB. The size of a block is 512B. Explain what a Direct Mapped Memory Cache is and how it works in this particular example.
a processor using 32-bit memory addresses and a fully associative cache memory that stores 32 bits of data for each address.what percent of the cache memory is spent on address and data valid information? a)12.5 % b)25 % c)50 % d)75 %
Suppose that a 64 Mega x 16 bits main memory is built using 16M x 8 bits chips of RAM and memory is word addressable. a. How many RAM chips are necessary? ______ b. How many RAM chips are needed for each memory word? _______ c. How many address bits are needed for each RAM chip? _______ d. How many address bits are needed for all memory? _______
Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
Q 1. Answer the following short questions. Support your answers with diagram, where needed: How the LIFO memory differs to FIFO Memory. Which type of addressing mode is used by the Instruction: ADD [BX+2], AX? What is the equivalent of a Binary number: 00110100011012 in octal and hexa-decimal. How much memory space is addressable (in bytes) by a microprocessor, if it uses 36 address lines? If Base address = A000H, Physical address = A0345H, then the offset add = ___________? Why address bus is unidirectional and data bus is bidirectional in 8086?
Consider a system that has multiple processors where each processor has its own cache, but main memory is shared among all processors.q.) Which cache write policy would you use?
We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.
Using multiple 4M × 8 RAM chips (see below) plus a decoder, construct theblock diagram of a 16M × 16 RAM system. Hint: 1 million = 2^20. Please answer the following questions.How many 4M × 8 RAM chips are needed?How many address lines does the memory system require?How many data lines does the memory system require? What kind of address decoder is required? Now design the system below. Be sure you label the memory systeminputs, Addr, R/W, and MemSel, and the system’s outputs D0~D15. Also label buswidths, and inputs and outputs of any required decoders. Put a star on the chipscontaining memory location 0.
What do you understand by bus system of computer, briefly describe. What do you understand by Address bus, data bus and control bus? State the function, significance and direction of signal flow for each. What do you understand by a 16 bit microprocessor? Give examples Given the contents of following register pairs, calculate the physical address of main memory location pointed by each: [CS]:[IP] = [1F0AH]:[15A6H] [SS]:[SP] = [82FFH]:[0FA1H]