A processor can address 65536 Bytes of memory. (i) Find the number of lines it must have in its address bus. (ii) If its address bus is increased by 4 lines, how much more memory capacity can it address?
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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Most Intel CPUs use the __________, in which each memory address is represented by two integers.
- Can a specific physical address have more than two logical addresses? Give your opinion with examples. Suppose you have a microprocessor which has 16MB of total physical memory. In this case what would be the size of the address bus?If a CPU issues a 32-bit address on the address bus, and the computer uses the high-order 12 bits to access the memory map, with the remaining address lines going directly to memory: a) Exactly how many pages of memory does this computer have? b) What is the size of each page?A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least___(bits)?.
- Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.Q.) How many blocks of main memory are there?Suppose that a microprocessor operates at 5MHz. How long does the bus cycle occupy, assuming no wait states are inserted?Suppose a byte-addressable computer using 4-way setassociative cache has 216 words of main memory (where each word is 32 bits) and a cache of 32 blocks, where each block is four words. Show the main memory address format for this machine. (Hint: Because this architecture is byte addressable, and the number of addresses is critical in determining the address format, you must convert everything to bytes.)
- For a microprocessor to operate, let assume that it requires 2MB of RAM and 7MB of ROM. What is the minimum number of address lines the microprocessor must support? Draw a memory map of the system, assuming that the addresses for the RAM are below the addresses for the ROM.Consider a 32 – bit microprocessor, with a 16 – bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor?What is the reachable memory space for a computer using a 12-bit address mechanism? What is the maximum amount of memory bits that this computer can have assuming memory cells are 4 bits in size?