A problem of register machines and computibility. "Initially, registers A and B contain x and y stones, respectively, with all other registers empty. Program the machine to leave x-y stones in register A unless that's a negative number, in which case it's to leave 0 stones there." Using register machine diagrams.
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A problem of register machines and computibility. "Initially, registers A and B contain x and y stones, respectively, with all other registers empty.
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- For the problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: add addi not beq lw sw 20% 20% 0% 25% 25% 10% In what fraction of all cycles is the data memory used?In what fraction of all cycles is the input of the sign-extend circuit needed? What is this circuit doing in cycles in which its input is not needed?Do you know what would happen if an instruction was rejected? When compared to a hardware-managed TLB, a software-managed TLB is quicker in the following scenarios:The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, Compare how Little’s and Amdahl’s law will work on it?
- Assume that the state of the 8088’s registers and memory just prior to the executionof each instruction in problem 15 is as follows: * in photos*What result is produced in the destination operand by executing instructions (a)through (k)? *only b,c,e,g* b) ADC SI, AX(c) INC BYTE PTR [0100H] (e) SBB DL, [0200H] (g) NEG BYTE PTR [DI]+0010HWhat would happen if an instruction was disobeyed, and why would that be the case? In the following scenarios, a TLB that is maintained by software is more efficient than one that is handled by hardware:2. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?
- Assume that the state of the 8088’s registers and memory just prior to the executionof each instruction in problem 15 is as follows: * in photos*What result is produced in the destination operand by executing instructions (a)through (k)? *only h through k* (h) MUL DX(i) IMUL BYTE PTR [BX+SI](j) DIV BYTE PTR [SI]+0030H(k) IDIV BYTE PTR [BX][SI]+0030HConsider the following register transfer statements for two 4-bit registers R1 and R2. xT: R1← R1+ R2 x' T: R1 ← R2 Every time that variable T = 1, either the content of R2 is added to the content of Rl if x = 1, or the content of R2 is transferred to R1 if x = 0. Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two 4-bit registers, a 4-bit adder, and a quadruple 2-to-1-llne multiplexer that selects the inputs to R l . In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1.The unique addresses assigned to the four registers (R11,R12,13,R14) of the I/O interface are equal to the XX3 , XX7 , XXB and XXF in Hex . Where XX is hex digits equal to your roll no . (if student is having roll no 45 than address are 453 ,457 ,45B , 45F in Hex ) .Show the well labeled external circuit that must be connected between and 12-bit I/O address from the CPU and the CS, RSI, and RS0 Inputs of the Interface.
- Explain what you mean by "pipelining" in the context of improving processor speed, and then determine how many cycles it will take to run five instructions assuming each part of the machine requires one cycle. First, we'll look at the situation a) without pipelining and b) with pipelining. There are four ways to do this: a, b, c, and d, all of which include pipelining.Suppose the logic blocks used to implement the processor as discussed in class have the following delays: Instr/Data Memory Access Register File Decode+Read Mux ALU Adder (outside ALU) Single gate delay Register read Register Write Sign Extend 250ps 150ps 25ps 200ps 150ps 5ps 30ps 20ps 50 a) How much time would you expect to take to execute an R-type instruction based on the details studied in class? b) How much time would you expect to take to execute an lw instruction based on the details studied in class? (0.4 c) Based on these two questions, is it possible to guess what would the (minimum) clock cycle time be of such a processor if the instructions are executed in one cycle? If yes, indicate it. If it is not, state the reason why not.Assuming the same instruction mix listed in Problem 7, what is the average execution time across all instructions?