Suppose the logic blocks used to implement the processor as discussed in class have the following delays: Instr/Data Memory Access Register File Decode+Read Mux ALU Adder (outside ALU) Single gate delay Register read Register Write Sign Extend 250ps 150ps 25ps 200ps 150ps 5ps 30ps 20ps 50 a) How much time would you expect to take to execute an R-type instruction based on the details studied in class? b) How much time would you expect to take to execute an lw instruction based on the details studied in class? (0.4 c) Based on these two questions, is it possible to guess what would the (minimum) clock cycle time be of such a processor if the instructions are executed in one cycle? If yes, indicate it. If it is not, state the reason why not.

Suppose the logic blocks used to implement the processor as discussed in class have the following delays: Instr/Data Memory Access Register File Decode+Read Mux ALU Adder (outside ALU) Single gate delay Register read Register Write Sign Extend 250ps 150ps 25ps 200ps 150ps 5ps 30ps 20ps 50 a) How much time would you expect to take to execute an R-type instruction based on the details studied in class? b) How much time would you expect to take to execute an lw instruction based on the details studied in class? (0.4 c) Based on these two questions, is it possible to guess what would the (minimum) clock cycle time be of such a processor if the instructions are executed in one cycle? If yes, indicate it. If it is not, state the reason why not.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
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Systems Architecture

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Computer Science

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9781305080195

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Stephen D. Burd

Publisher:

Cengage Learning

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Instr/Data Memory Access	Register File Decode+Read	Mux	ALU	Adder (outside ALU)	Single gate delay	Register read	Register Write	Sign Extend
250ps	150ps	25ps	200ps	150ps	5ps	30ps	20ps	50