(a) What is the special task of ECX register?(b) What is cache? Explain cache miss and cache hit ?(c) A computer program has three types of instructions. 40% instructioprogram are load instructions, 30% instructions of the program are arit.operations, and the rest of the instructions floating point instructions. Einstruction takes 3 clock cycles to execute. Each arithmetic operation tacycle to execute. And Each floating point instructions takes 15 clock cycexecute. The Processor is 2.3 GHz. The program completes its executionseconds. What is the total number of instructions in the program? (5 poirParagraph+ vAdd a FileRecord Audio

THIS IS A MULTIPLE-QUESTION-BASED PROBLEM. ONLY THE FIRST QUESTION IS SOLVED. KINDLY SEND THE…

Answered: (a) What is the special task of ECX…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex. addi $t0, $Zero, -50 andi $t1, $t0, 7 Loop:and $t1,$t0,$t1 Sw $t0, 40 ($t1) Bne $t1,$ zero, Loop 2- What is the MIPS assembly instruction for the following machine code? 0x8C220004
2- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex. addi $t0, $Zero, -50 andi $t1, $t0, 7 Loop:and $t1,$t0,$t1 Sw $t0, 40 ($t1) Bne $t1,$ zero, Loop
6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…
I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?
a. How many bits are needed for the opcode of memory unit with 24 bits per word and instruction set consists of 199 different operations? b. How many bits are left for the address part of the instruction?
What is the point of using cache memory if we already have volatile RAM (Random Access Memory)?Transistors are used in both random-access memory (RAM) and cache memory. Is it conceivable, if at all possible, to employ just one kind of memory to carry out all of a computer's functions?
(ASM) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[f] = A[(i-h)+j] + g;
Which statement is correct for the memory segments in 8086 microprocessor? a. For Stack segment, the offset address can be a direct value. b. The offset address for program instructions is taken from SP register. c. Variables created in the Assembly program are stored in Data segment. d. Segment address for executing sub-routines is taken from ES register.
For the following MIPS assembly instructions what is the corresponding C statement? Assume that variables f,g,h,i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Add comments for each line to describe what each instruction does. addi $t0, $s6, 4 # $t0 = &A+4 = &A[1] add $t1, $s6, $zero # sw $t1, 0($t0) # lw $t0, 0($t0) # add $s0, $t1, $t0 #
Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
For the MIPS assembly instructions below, what is the corresponding C statement?Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and$s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t1, $s1, 2add $t1, $t1, $s6lw $t1, 0($t1)sub $t0, $s3, $s4sll $t0, $t0, 2add $t0, $t0, $s7lw $t0, 0($t0)add $t1, $t1, $t0sll $t0, $s0, 2add $t0, $t0, $s7sw $t1, 0($t0)
lw r1,12(r7)lw r2,16(r7)add r1,r1,r2sw r1,4(r5)a. Identify and describe all the data dependencies.b. How many clock cycles does it take to execute this code without any pipelining?c. How many clock cycles with pipelining, but no bypassing (stalls cause the pipeline to wait until previous instruction is finished)?

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