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address 32-bits) has 16-KB (only L1-data) direct mapped cache. If the cache line size is 64-Bytes how many bits will be used for tag, index and offset? If a memory address is 0x00222222, what will be the tag, index and offset for this address (in binary, hex, decimal)? What will be the total size of cache including tag and V-bit?

address 32-bits) has 16-KB (only L1-data) direct mapped cache. If the cache line size is 64-Bytes how many bits will be used for tag, index and offset? If a memory address is 0x00222222, what will be the tag, index and offset for this address (in binary, hex, decimal)? What will be the total size of cache including tag and V-bit?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Assume your 32-bit computer (memory address 32-bits) has 16-KB (only L1-data) direct mapped cache. If the cache line size is 64-Bytes how many bits will be used for tag, index and offset? If a memory address is 0x00222222, what will be the tag, index and offset for this address (in binary, hex, decimal)? What will be the total size of cache including tag and V-bit?  

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