Assume your 32-bit computer (memory address 32-bits) has 16-KB (only L1-data) direct mapped cache. If the cache line size is 64-Bytes how many bits will be used for tag, index and offset? If a memory address is 0x00222222, what will be the tag, index and offset for this address (in binary, hex, decimal)? What will be the total size of cache including tag and V-bit?

Assume your 32-bit computer (memory address 32-bits) has 16-KB (only L1-data) direct mapped cache. If the cache line size is 64-Bytes how many bits will be used for tag, index and offset? If a memory address is 0x00222222, what will be the tag, index and offset for this address (in binary, hex, decimal)? What will be the total size of cache including tag and V-bit?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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