An 'instruction fetch/read' results in three sets of numbers that go to the Registers Block as studied in class. These three numbers in the instruction represent bits 25-21 for 'Read Register 1', bits 20-16 for 'Read Register 2', and bits 15-11 for the 'Write Register'. What does the 5 bits width of each of these indicate? Choose the best answer. That each word is 32 bits long That there are 15 registers that can be addressed in this architecture That there are 32 registers that can be addressed in this architecture O That the word is 15 bits long in this architecture

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
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Chapter1: Computer Networks And The Internet
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An 'instruction fetch/read' results in three sets of numbers that go to the Registers
Block as studied in class. These three numbers in the instruction represent bits 25-21
for 'Read Register 1' bits 20-16 for 'Read Register 2', and bits 15-11 for the 'Write
Register'.
What does the 5 bits width of each of these indicate?
Choose the best answer.
That each word is 32 bits long
That there are 15 registers that can be addressed in this architecture
That there are 32 registers that can be addressed in this architecture
O That the word is 15 bits long in this architecture
Transcribed Image Text:An 'instruction fetch/read' results in three sets of numbers that go to the Registers Block as studied in class. These three numbers in the instruction represent bits 25-21 for 'Read Register 1' bits 20-16 for 'Read Register 2', and bits 15-11 for the 'Write Register'. What does the 5 bits width of each of these indicate? Choose the best answer. That each word is 32 bits long That there are 15 registers that can be addressed in this architecture That there are 32 registers that can be addressed in this architecture O That the word is 15 bits long in this architecture
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