Assuming that we only care about the output at out2, what modification to the given circuit would you suggest so that the circuit satisfies hold constraint while the functionality at out2 remains unchanged? Draw your updated circuit below. You may (or may not) use an additional NOT gate apart from which no extra components are provided. You are free to move around the gates. What is the highest clock frequency you can use for the updated circuit? There is no one correct answer for this question, you can be creative as long as the output at out2 is correct. Please note that out2 changes three clock edges after the input changes, this needs to be maintained in your updated circuit as well.

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